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user?s manual, v2.2, jan. 2004 microcontrollers never stop thinking. XC161 volume 2 (of 2): peripheral units 16-bit s i ngl e-chi p micro c on troll e r with c166sv2 core
edition 2004-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
user?s manual, v2.2, jan. 2004 microcontrollers never stop thinking. XC161 volume 2 (of 2): peripheral units 16-bit s i ngl e-chi p micro c on troll e r with c166sv2 core
template: mc_tmplt_a5.fm / 3 / 2003-09-01 controller area network (can): license of robert bosch gmbh XC161 volume 2 (of 2): peripheral units revision history: v2.2, 2004-01 previous version: v2.2, 2003-09 (pre-release) v2.1, 2003-06 v2.0, 2003-03 v1.1, 2002-02 (draft manual) v1.0, 2001-04 (draft manual) page subjects (major changes since version v2.1) 1) 1) in order to create the current version v2.2 of this manual, the layout of several graphics and text structures has been adapted to company documentation rules. the contents have not been changed otherwise, except for the pre-release note on page 1-2 or obvious typographical errors. 14-1 ff timer block description introduced 14-7 phrasing improved 14-26 figure corrected 14-27 prescaler table reworked 14-29 timer register description added 14-35 phrasing improved 14-50 prescaler table reworked 14-53 timer register description added 17-1 ff register names adapted we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-1 v2.2, 2004-01 this user?s manual consists of two volumes, ?system units? and ?peripheral units?. for your convenience this table of contents (and also the keyword index) lists both volumes, so can immediately find the reference to the desired section in the corresponding document ([1] or [2]). 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1] 1.1 members of the 16-bit microcontroller family . . . . . . . . . . . . . . . . . . . 1-3 [1] 1.2 summary of basic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1] 1.3 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1] 1.4 naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1] 2 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1] 2.1 basic cpu concepts and optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1] 2.1.1 high instruction bandwidth/fast execution . . . . . . . . . . . . . . . . . . . 2-4 [1] 2.1.2 powerful execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1] 2.1.3 high performance branch-, call-, and loop-processing . . . . . . . . . 2-6 [1] 2.1.4 consistent and optimized instruction formats . . . . . . . . . . . . . . . . 2-7 [1] 2.1.5 programmable multiple priority interrupt system . . . . . . . . . . . . . . 2-8 [1] 2.1.6 interfaces to system resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1] 2.2 on-chip system resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1] 2.3 on-chip peripheral blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 [1] 2.4 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1] 2.5 power management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1] 2.6 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 [1] 2.7 protected bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1] 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1] 3.1 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1] 3.2 special function register areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1] 3.3 data memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 [1] 3.4 program memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1] 3.5 system stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1] 3.6 io areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 [1] 3.7 external memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1] 3.8 crossing memory boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1] 3.9 the on-chip program flash module . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1] 3.9.1 flash operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] 3.9.2 command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 [1] 3.9.3 error correction and data integrity . . . . . . . . . . . . . . . . . . . . . . . . 3-25 [1] 3.9.4 protection and security features . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 [1] 3.9.5 flash status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 [1] 3.9.6 operation control and error handling . . . . . . . . . . . . . . . . . . . . . . 3-35 [1]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-2 v2.2, 2004-01 3.10 program memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 [1] 3.10.1 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 [1] 3.10.2 flash memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 [1] 3.10.3 imb control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 [1] 4 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1] 4.1 components of the cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1] 4.2 instruction fetch and program flow control . . . . . . . . . . . . . . . . . . . . 4-5 [1] 4.2.1 branch detection and branch prediction rules . . . . . . . . . . . . . . . . 4-7 [1] 4.2.2 correctly predicted instruction flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1] 4.2.3 incorrectly predicted instruction flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1] 4.3 instruction processing pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1] 4.3.1 pipeline conflicts using general purpose registers . . . . . . . . . . . 4-13 [1] 4.3.2 pipeline conflicts using indirect addressing modes . . . . . . . . . . . 4-15 [1] 4.3.3 pipeline conflicts due to memory bandwidth . . . . . . . . . . . . . . . . 4-17 [1] 4.3.4 pipeline conflicts caused by cpu-sfr updates . . . . . . . . . . . . . 4-20 [1] 4.4 cpu configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1] 4.5 use of general purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1] 4.5.1 gpr addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1] 4.5.2 context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1] 4.6 code addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 [1] 4.7 data addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1] 4.7.1 short addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1] 4.7.2 long addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1] 4.7.3 indirect addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 [1] 4.7.4 dsp addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 [1] 4.7.5 the system stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 [1] 4.8 standard data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 [1] 4.8.1 16-bit adder/subtracter, barrel shifter, and 16-bit logic unit . . . . 4-61 [1] 4.8.2 bit manipulation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 [1] 4.8.3 multiply and divide unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 [1] 4.9 dsp data processing (mac unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 [1] 4.9.1 representation of numbers and rounding . . . . . . . . . . . . . . . . . . 4-66 [1] 4.9.2 the 16-bit by 16-bit signed/unsigned multiplier and scaler . . . . . 4-67 [1] 4.9.3 concatenation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1] 4.9.4 one-bit scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1] 4.9.5 the 40-bit adder/subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1] 4.9.6 the data limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1] 4.9.7 the accumulator shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1] 4.9.8 the 40-bit signed accumulator register . . . . . . . . . . . . . . . . . . . . 4-69 [1] 4.9.9 the mac unit status word msw . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 [1] 4.9.10 the repeat counter mrw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 [1] 4.10 constant registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74 [1]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-3 v2.2, 2004-01 5 interrupt and trap functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1] 5.1 interrupt system structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1] 5.2 interrupt arbitration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 [1] 5.3 interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1] 5.4 operation of the peripheral event controller channels . . . . . . . . . . 5-18 [1] 5.4.1 the pec source and destination pointers . . . . . . . . . . . . . . . . . . 5-22 [1] 5.4.2 pec transfer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 [1] 5.4.3 channel link mode for data chaining . . . . . . . . . . . . . . . . . . . . . . 5-26 [1] 5.4.4 pec interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 [1] 5.5 prioritization of interrupt and pec service requests . . . . . . . . . . . . 5-29 [1] 5.6 context switching and saving status . . . . . . . . . . . . . . . . . . . . . . . . 5-31 [1] 5.7 interrupt node sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 [1] 5.8 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1] 5.9 ocds requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 [1] 5.10 service request latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1] 5.11 trap functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 [1] 6 general system control functions . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1] 6.1 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1] 6.1.1 reset sources and phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1] 6.1.2 status after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1] 6.1.3 application-specific initialization routine . . . . . . . . . . . . . . . . . . . 6-11 [1] 6.1.4 system startup configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 [1] 6.1.5 hardware configuration in external start mode . . . . . . . . . . . . . . 6-18 [1] 6.1.6 default configuration in single-chip mode . . . . . . . . . . . . . . . . . . 6-23 [1] 6.1.7 reset behavior control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 [1] 6.2 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 [1] 6.2.1 oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 [1] 6.2.2 clock generation and frequency control . . . . . . . . . . . . . . . . . . . 6-30 [1] 6.2.3 clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 [1] 6.2.4 oscillator watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1] 6.2.5 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1] 6.2.6 generation of an external clock signal . . . . . . . . . . . . . . . . . . . . 6-39 [1] 6.3 central system control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 [1] 6.3.1 status indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 [1] 6.3.2 reset source indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 [1] 6.3.3 peripheral shutdown handshake . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1] 6.3.4 flexible peripheral management . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1] 6.3.5 debug system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 [1] 6.3.6 register security mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 [1] 6.4 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 [1] 6.5 identification control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 [1]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-4 v2.2, 2004-01 7 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1] 7.1 input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1] 7.2 output driver control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 [1] 7.3 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 [1] 7.4 port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1] 7.5 port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 [1] 7.6 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 [1] 7.7 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 [1] 7.8 port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 [1] 7.9 port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 [1] 7.10 port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 [1] 7.11 port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65 [1] 7.12 port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-72 [1] 7.13 port 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-82 [1] 8 dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1] 9 the external bus controller ebc . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1] 9.1 external bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1] 9.2 timing principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1] 9.2.1 basic bus cycle protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1] 9.2.1.1 demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 [1] 9.2.1.2 multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1] 9.2.2 bus cycle phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] 9.2.2.1 a phase - cs change phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] 9.2.2.2 b phase - address setup/ale phase . . . . . . . . . . . . . . . . . . . . . 9-7 [1] 9.2.2.3 c phase - delay phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] 9.2.2.4 d phase - write data setup/mux tristate phase . . . . . . . . . . . . 9-7 [1] 9.2.2.5 e phase - rd /wr command phase . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] 9.2.2.6 f phase - address/write data hold phase . . . . . . . . . . . . . . . . . 9-8 [1] 9.2.3 bus cycle examples: fastest access cycles . . . . . . . . . . . . . . . . . 9-8 [1] 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1] 9.3.1 configuration register overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1] 9.3.2 the ebc mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 [1] 9.3.3 the ebc mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 [1] 9.3.4 the timing configuration registers tconcsx . . . . . . . . . . . . . . 9-15 [1] 9.3.5 the function configuration registers fconcsx . . . . . . . . . . . . . 9-16 [1] 9.3.6 the address window selection registers addrselx . . . . . . . . . 9-18 [1] 9.3.6.1 definition of address areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 [1] 9.3.6.2 address window arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 [1] 9.3.7 ready controlled bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1] 9.3.7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1] 9.3.7.2 the synchronous/asynchronous ready . . . . . . . . . . . . . . . . . 9-22 [1]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-5 v2.2, 2004-01 9.3.7.3 combining the ready function with predefined wait states . 9-22 [1] 9.3.8 access control to twincan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 [1] 9.3.9 external bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1] 9.3.9.1 initialization of arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1] 9.3.9.2 arbitration master scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1] 9.3.9.3 arbitration slave scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 [1] 9.3.9.4 bus lock function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1] 9.3.9.5 direct master slave connection . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1] 9.3.10 shutdown control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 [1] 9.4 lxbus access control and signal generation . . . . . . . . . . . . . . . . . 9-29 [1] 9.5 ebc register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 [1] 10 the bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1] 10.1 entering the bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1] 10.2 loading the startup code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1] 10.3 exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1] 10.4 choosing the baudrate for the bsl . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 [1] 11 debug system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1] 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1] 11.2 debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 [1] 11.3 ocds module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 [1] 11.3.1 debug events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 [1] 11.3.2 debug actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 [1] 11.4 cerberus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1] 11.4.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1] 11.5 emulation device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 [1] 12 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1] 13 device specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1] 14 the general purpose timer units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2] 14.1 timer block gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 [2] 14.1.1 gpt1 core timer t3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 [2] 14.1.2 gpt1 core timer t3 operating modes . . . . . . . . . . . . . . . . . . . . . 14-8 [2] 14.1.3 gpt1 auxiliary timers t2/t4 control . . . . . . . . . . . . . . . . . . . . . 14-15 [2] 14.1.4 gpt1 auxiliary timers t2/t4 operating modes . . . . . . . . . . . . . 14-18 [2] 14.1.5 gpt1 clock signal control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 [2] 14.1.6 gpt1 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 [2] 14.1.7 interrupt control for gpt1 timers . . . . . . . . . . . . . . . . . . . . . . . . 14-30 [2] 14.2 timer block gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 [2] 14.2.1 gpt2 core timer t6 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33 [2] 14.2.2 gpt2 core timer t6 operating modes . . . . . . . . . . . . . . . . . . . . 14-36 [2]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-6 v2.2, 2004-01 14.2.3 gpt2 auxiliary timer t5 control . . . . . . . . . . . . . . . . . . . . . . . . 14-39 [2] 14.2.4 gpt2 auxiliary timer t5 operating modes . . . . . . . . . . . . . . . . . 14-41 [2] 14.2.5 gpt2 register caprel operating modes . . . . . . . . . . . . . . . . . 14-45 [2] 14.2.6 gpt2 clock signal control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50 [2] 14.2.7 gpt2 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53 [2] 14.2.8 interrupt control for gpt2 timers and caprel . . . . . . . . . . . . . 14-54 [2] 14.3 interfaces of the gpt module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-55 [2] 15 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2] 15.1 defining the rtc time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 [2] 15.2 rtc run control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [2] 15.3 rtc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [2] 15.3.1 48-bit timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2] 15.3.2 system clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2] 15.3.3 cyclic interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2] 15.4 rtc interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [2] 16 the analog/digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2] 16.1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2] 16.1.1 compatibility mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2] 16.1.2 enhanced mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [2] 16.2 adc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [2] 16.2.1 fixed channel conversion modes . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [2] 16.2.2 auto scan conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 [2] 16.2.3 wait for read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 [2] 16.2.4 channel injection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 [2] 16.3 automatic calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 [2] 16.4 conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 [2] 16.5 a/d converter interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 [2] 16.6 interfaces of the adc module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [2] 17 capture/compare units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2] 17.1 the capcom timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [2] 17.2 capcom timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [2] 17.3 capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [2] 17.4 capture mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [2] 17.5 compare mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [2] 17.5.1 compare mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2] 17.5.2 compare mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2] 17.5.3 compare mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2] 17.5.4 compare mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2] 17.5.5 double-register compare mode . . . . . . . . . . . . . . . . . . . . . . . . 17-22 [2] 17.6 compare output signal generation . . . . . . . . . . . . . . . . . . . . . . . . 17-25 [2] 17.7 single event operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 [2]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-7 v2.2, 2004-01 17.8 staggered and non-staggered operation . . . . . . . . . . . . . . . . . . . . 17-29 [2] 17.9 capcom interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 [2] 17.10 external input signal requirements . . . . . . . . . . . . . . . . . . . . . . . . 17-36 [2] 17.11 interfaces of the capcom units . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 [2] 18 asynchronous/synchronous serial interface (asc) . . . . . . . . . . 18-1 [2] 18.1 operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 [2] 18.2 asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 [2] 18.2.1 asynchronous data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 [2] 18.2.2 asynchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2] 18.2.3 transmit fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2] 18.2.4 asynchronous reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2] 18.2.5 receive fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2] 18.2.6 fifo transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 [2] 18.2.7 irda mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 [2] 18.2.8 rxd/txd data path selection in asynchronous modes . . . . . . . 18-17 [2] 18.3 synchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 [2] 18.3.1 synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2] 18.3.2 synchronous reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2] 18.3.3 synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2] 18.4 baudrate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2] 18.4.1 baudrate in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2] 18.4.2 baudrate in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 [2] 18.5 autobaud detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2] 18.5.1 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2] 18.5.2 serial frames for autobaud detection . . . . . . . . . . . . . . . . . . . . . 18-28 [2] 18.5.3 baudrate selection and calculation . . . . . . . . . . . . . . . . . . . . . . . 18-29 [2] 18.5.4 overwriting registers on successful autobaud detection . . . . . 18-33 [2] 18.6 hardware error detection capabilities . . . . . . . . . . . . . . . . . . . . . . 18-34 [2] 18.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35 [2] 18.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 [2] 18.9 interfaces of the asc modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56 [2] 19 high-speed synchronous serial interface (ssc) . . . . . . . . . . . . 19-1 [2] 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2] 19.2 operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2] 19.2.1 operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 [2] 19.2.2 full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 [2] 19.2.3 half-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 [2] 19.2.4 continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2] 19.2.5 baudrate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2] 19.2.6 error detection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 [2] 19.2.7 ssc register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 [2]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-8 v2.2, 2004-01 19.2.8 port configuration requirements . . . . . . . . . . . . . . . . . . . . . . . . 19-17 [2] 19.3 interfaces of the ssc modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 [2] 20 iic-bus module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2] 20.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [2] 20.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 [2] 20.3 iic-bus module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2] 20.3.1 operation in single-master mode . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2] 20.3.2 operation in multimaster mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2] 20.3.3 operation in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 [2] 20.3.4 transmit/receive buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2] 20.3.5 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 [2] 20.3.6 notes for programming the iic-bus module . . . . . . . . . . . . . . . . 20-16 [2] 20.4 interrupt request operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 [2] 20.5 port connection and configuration . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 [2] 20.6 interfaces of the iic-bus module . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 [2] 20.7 iic-bus overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 [2] 21 twincan module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2] 21.1 kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2] 21.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2] 21.1.2 twincan control shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2] 21.1.2.1 initialization processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2] 21.1.2.2 interrupt request compressor . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 [2] 21.1.2.3 global control and status logic . . . . . . . . . . . . . . . . . . . . . . . . 21-6 [2] 21.1.3 can node control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2] 21.1.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2] 21.1.3.2 timing control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 [2] 21.1.3.3 bitstream processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2] 21.1.3.4 error handling logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2] 21.1.3.5 node interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2] 21.1.3.6 message interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2] 21.1.3.7 interrupt indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2] 21.1.4 message handling unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 [2] 21.1.4.1 arbitration and acceptance mask register . . . . . . . . . . . . . . . 21-16 [2] 21.1.4.2 handling of remote and data frames . . . . . . . . . . . . . . . . . . 21-17 [2] 21.1.4.3 handling of transmit message objects . . . . . . . . . . . . . . . . . . 21-18 [2] 21.1.4.4 handling of receive message objects . . . . . . . . . . . . . . . . . . 21-21 [2] 21.1.4.5 single data transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 [2] 21.1.5 can message object buffer (fifo) . . . . . . . . . . . . . . . . . . . . . . 21-24 [2] 21.1.5.1 buffer access by the can controller . . . . . . . . . . . . . . . . . . . 21-26 [2] 21.1.5.2 buffer access by the cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 [2] 21.1.6 gateway message handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 [2]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-9 v2.2, 2004-01 21.1.6.1 normal gateway mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 [2] 21.1.6.2 normal gateway with fifo buffering . . . . . . . . . . . . . . . . . . . 21-33 [2] 21.1.6.3 shared gateway mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36 [2] 21.1.7 programming the twincan module . . . . . . . . . . . . . . . . . . . . . . 21-40 [2] 21.1.7.1 configuration of can node a/b . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2] 21.1.7.2 initialization of message objects . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2] 21.1.7.3 controlling a message transfer . . . . . . . . . . . . . . . . . . . . . . . 21-41 [2] 21.1.8 loop-back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 [2] 21.1.9 single transmission try functionality . . . . . . . . . . . . . . . . . . . . 21-45 [2] 21.1.10 module clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 [2] 21.2 twincan register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2] 21.2.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2] 21.2.2 can node a/b registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49 [2] 21.2.3 can message object registers . . . . . . . . . . . . . . . . . . . . . . . . . 21-64 [2] 21.2.4 global can control/status registers . . . . . . . . . . . . . . . . . . . . . 21-80 [2] 21.3 XC161 module implementation details . . . . . . . . . . . . . . . . . . . . . . 21-82 [2] 21.3.1 interfaces of the twincan module . . . . . . . . . . . . . . . . . . . . . . . 21-82 [2] 21.3.2 twincan module related external registers . . . . . . . . . . . . . . . 21-83 [2] 21.3.2.1 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-84 [2] 21.3.2.2 port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-85 [2] 21.3.2.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-90 [2] 21.3.3 register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-91 [2] 22 serial data link module sdlm . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2] 22.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2] 22.2 sdlm kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2] 22.2.1 j1850 concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2] 22.2.1.1 frame format basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 [2] 22.2.1.2 j1850 bits and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2] 22.2.1.3 frame arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2] 22.2.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2] 22.2.2.1 4x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 [2] 22.2.2.2 break operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 [2] 22.2.3 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 [2] 22.2.3.1 message operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [2] 22.2.3.2 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [2] 22.2.3.3 transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2] 22.2.4 in-frame response (ifr) operation . . . . . . . . . . . . . . . . . . . . . . 22-12 [2] 22.2.5 block mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 [2] 22.2.6 bus access in fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 [2] 22.2.7 flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 [2] 22.2.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 [2] 22.2.7.2 transmission control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17 [2]
XC161 derivatives peripheral units (vol. 2 of 2) table of contents page user?s manual i-10 v2.2, 2004-01 22.2.7.3 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20 [2] 22.2.8 ifr handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2] 22.2.8.1 ifr types 1, 2 via ifrval . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2] 22.3 sdlm register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 [2] 22.3.1 global control and timing registers . . . . . . . . . . . . . . . . . . . . . . 22-24 [2] 22.4 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 [2] 22.4.1 transmission related registers . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 [2] 22.4.2 reception related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-43 [2] 22.5 sdlm module register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 [2] 22.6 XC161 module implementation details . . . . . . . . . . . . . . . . . . . . . . 22-51 [2] 22.6.1 interfaces of the sdlm module . . . . . . . . . . . . . . . . . . . . . . . . . . 22-51 [2] 22.6.2 sdlm module related external registers . . . . . . . . . . . . . . . . . 22-53 [2] 22.6.2.1 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54 [2] 22.6.2.2 port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-55 [2] 22.6.2.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-60 [2] 23 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2] 23.1 pd+bus peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2] 23.2 lxbus peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 [2] keyword index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 [1+2]
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-1 v2.2, 2004-01 gpt_x1, v2.0 14 the general purpose timer units the general purpose timer unit blocks gpt1 and gpt2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. they incorporate five 16-bit timers that are grouped into the two timer blocks gpt1 and gpt2. each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. each block has alternate input/output functions and specific interrupts associated with it. block gpt1 contains three timers/counters: the core timer t3 and the two auxiliary timers t2 and t4. the maximum resolution is f gpt /4. the auxiliary timers of gpt1 may optionally be configured as reload or capture registers for the core timer. these registers are listed in section 14.1.6 . f gpt /4 maximum resolution 3 independent timers/counters timers/counters can be concatenated 4 operating modes: ? timer mode ? gated timer mode ? counter mode ? incremental interface mode reload and capture functionality separate interrupt lines block gpt2 contains two timers/counters: the core timer t6 and the auxiliary timer t5. the maximum resolution is f gpt /2. an additional capture/reload register (caprel) supports capture and reload operation with extended functionality. these registers are listed in section 14.2.7 . the core timer t6 may be concatenated with timers of the capcom units (t0, t1, t7, and t8). the following list summarizes the features which are supported: f gpt /2 maximum resolution 2 independent timers/counters timers/counters can be concatenated 3 operating modes: ? timer mode ? gated timer mode ? counter mode extended capture/reload functions via 16-bit capture/reload register caprel separate interrupt lines
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-2 v2.2, 2004-01 gpt_x1, v2.0 14.1 timer block gpt1 from a programmer?s point of view, the gpt1 block is composed of a set of sfrs as summarized below. those portions of port and direction registers which are used for alternate functions by the gpt1 block are shaded. figure 14-1 sfrs associated with timer block gpt1 all three timers of block gpt1 (t2, t3, t4) can run in one of 4 basic modes: timer mode, gated timer mode, counter mode, or incremental interface mode. all timers can count up or down. each timer of gpt1 is controlled by a separate control register txcon. each timer has an input pin txin (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. the count direction (up/down) may be programmed via software or may be dynamically altered by a signal at the external up/down control input txeud (alternate pin function). an overflow/underflow of core timer t3 is indicated by the output toggle latch t3otl, whose state may be output on the associated pin t3out (alternate pin function). the auxiliary timers t2 and t4 may additionally be concatenated with the core timer t3 (through t3otl) or may be used as capture or reload registers for the core timer t3. the current contents of each timer can be read or modified by the cpu by accessing the corresponding timer count registers t2, t3, or t4, located in the non-bitaddressable sfr space (see section 14.1.6 ). when any of the timer registers is written to by the cpu in the state immediately preceding a timer increment, decrement, reload, or capture operation, the cpu write operation has priority in order to guarantee correct results. mc_gpt0100_registers.vsd data registers control registers port registers t2 t2con t2ic t3 t3con t3ic t4 t4con t4ic odp3 dp3 p3 e p5 p5didis altsel0p3 e interrupt control syscon3 tx gpt1 timer x register txcon gpt1 timer x control register txic g pt1 tim er x interrupt ctrl. reg. sysco n3 system ctrl. reg. 3 (per. m gm t.) odp3 port 3 open drain control register dp3 port 3 direction control register p3 port 3 data register altsel0p3 port 3 alternate output select reg. p5 port 5 data register p5didis port 5 digital input disable reg.
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-3 v2.2, 2004-01 gpt_x1, v2.0 the interrupts of gpt1 are controlled through the interrupt control registers txic. these registers are not part of the gpt1 block. the input and output lines of gpt1 are connected to pins of ports p3 and p5. the control registers for the port functions are located in the respective port modules. note: the timing requirements for external input signals can be found in section 14.1.5 , section 14.3 summarizes the module interface signals, including pins. figure 14-2 gpt1 block diagram (n = 2 ? 5) t3 mode control 2 n : 1 f gpt t2 mode control aux. timer t2 reload capture t4 mode control aux. timer t4 reload capture core ti mer t3 t3otl u/d t2eud t2in t3in t3eud t4in t4eud toggle latch u/d u/d interrupt request (t2irq) interrupt request (t3irq) interrupt request (t4irq) mc_gpt0101_bldiax1.vsd t3out basic clock t3con.bps1
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-4 v2.2, 2004-01 gpt_x1, v2.0 14.1.1 gpt1 core timer t3 control the current contents of the core timer t3 are reflected by its count register t3. this register can also be written to by the cpu, for example, to set the initial start value. the core timer t3 is configured and controlled via its bitaddressable control register t3con. gpt12e_t3con timer 3 control register sfr (ff42 h /a1 h ) reset value: 0000 h 1514131211109876543210 t3 r dir t3 ch dir t3 ed ge bps1 t3 otl t3 oe t3 ude t3 ud t3r t3m t3i rh rwh rwh rw rwh rw rw rw rw rw rw field bits typ description t3rdir 15 rh timer t3 rotation direction flag 0 timer t3 counts up 1 timer t3 counts down t3chdir 14 rwh timer t3 count direction change flag this bit is set each time the count direction of timer t3 changes. t3chdir must be cleared by sw. 0 no change of count direction was detected 1 a change of count direction was detected t3edge 13 rwh timer t3 edge detection flag the bit is set each time a count edge is detected. t3edge must be cleared by sw. 0 no count edge was detected 1 a count edge was detected bps1 [12:11] rw gpt1 block prescaler control selects the basic clock for block gpt1 (see also section 14.1.5 ) 00 f gpt /8 01 f gpt /4 10 f gpt /32 11 f gpt /16 t3otl 10 rwh timer t3 overflow toggle latch toggles on each overflow/underflow of t3. can be set or reset by software (see separate description)
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-5 v2.2, 2004-01 gpt_x1, v2.0 t3oe 9rw overflow/underflow output enable 0 alternate output function disabled 1 state of t3 toggle latch is output on pin t3out t3ude 8rw timer t3 external up/down enable 0 input t3eud is disconnected 1 direction influenced by input t3eud 1) t3ud 7rw timer t3 up/down control 1) t3r 6rw timer t3 run bit 0 timer t3 stops 1timer t3 runs t3m [5:3] rw timer t3 mode control (basic operating mode) 000 timer mode 001 counter mode 010 gated timer mode with gate active low 011 gated timer mode with gate active high 100 reserved. do not use this combination. 101 reserved. do not use this combination. 110 incremental interface mode (rotation detection mode) 111 incremental interface mode (edge detection mode) t3i [2:0] rw timer t3 input parameter selection depends on the operating mode, see respective sections for encoding: table 14-7 for timer mode and gated timer mode table 14-2 for counter mode table 14-3 for incremental interface mode 1) see table 14-1 for encoding of bits t3ud and t3eud. field bits typ description
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-6 v2.2, 2004-01 gpt_x1, v2.0 timer t3 run control the core timer t3 can be started or stopped by software through bit t3r (timer t3 run bit). this bit is relevant in all operating modes of t3. setting bit t3r will start the timer, clearing bit t3r stops the timer. in gated timer mode, the timer will only run if t3r = 1 and the gate is active (high or low, as programmed). note: when bit t2rc or t4rc in timer control register t2con or t4con is set, bit t3r will also control (start and stop) the auxiliary timer(s) t2 and/or t4. count direction control the count direction of the gpt1 timers (core timer and auxiliary timers) can be controlled either by software or by the external input pin txeud (timer tx external up/down control input). these options are selected by bits txud and txude in the respective control register txcon. when the up/down control is provided by software (bit txude = 0), the count direction can be altered by setting or clearing bit txud. when bit txude = 1, pin txeud is selected to be the controlling source of the count direction. however, bit txud can still be used to reverse the actual count direction, as shown in table 14-1 . the count direction can be changed regardless of whether or not the timer is running. note: when pin txeud is used as external count direction control input, it must be configured as input (its corresponding direction control bit must be cleared). table 14-1 gpt1 timer count direction control pin txeud bit txude bit txud count direction bit txrdir x 00count up0 x 0 1 count down 1 0 10count up0 1 1 0 count down 1 0 1 1 count down 1 1 11count up0
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-7 v2.2, 2004-01 gpt_x1, v2.0 timer 3 output toggle latch the overflow/underflow signal of timer t3 is connected to a block named ?toggle latch?, shown in the timer mode diagrams. figure 14-3 illustrates the details of this block. an overflow or underflow of t3 will clock two latches: the first latch represents bit t3otl in control register t3con. the second latch is an internal latch toggled by t3otl?s output. both latch outputs are connected to the input control blocks of the auxiliary timers t2 and t4. the output level of the shadow latch will match the output level of t3otl, but is delayed by one clock cycle. when the t3otl value changes, this will result in a temporarily different output level from t3otl and the shadow latch, which can trigger the selected count event in t2 and/or t4. when software writes to t3otl, both latches are set or cleared simultaneously. in this case, both signals to the auxiliary timers carry the same level and no edge will be detected. bit t3oe (overflow/underflow output enable) in register t3con enables the state of t3otl to be monitored via an external pin t3out. when t3otl is linked to an external port pin (must be configured as output), t3out can be used to control external hw. if t3oe = 1, pin t3out outputs the state of t3otl. if t3oe = 0, pin t3out outputs a high level (as long as the t3out alternate function is selected for the port pin). the trigger signals can serve as an input for the counter function or as a trigger source for the reload function of the auxiliary timers t2 and t4. as can be seen from figure 14-3 , when latch t3otl is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. therefore, no trigger condition is detected by t2/t4 in this case. figure 14-3 block diagram of the toggle latch logic of core timer t3 mc_gpt0106_otl.vsd toggle latch logic txout set/clear (sw ) core timer overflow/ underflow shadow latch 1 0 mux 1 txoe txotl to port logic to aux. timer input logic
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-8 v2.2, 2004-01 gpt_x1, v2.0 14.1.2 gpt1 core timer t3 operating modes timer 3 in timer mode timer mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 000 b . in timer mode, t3 is clocked with the module?s input clock f gpt divided by two programmable prescalers controlled by bitfields bps1 and t3i in register t3con. please see section 14.1.5 for details on the input clock options. figure 14-4 block diagram of core timer t3 in timer mode prescaler core timer t3 toggle latch mcb05391 bps1 t3i mux up/down 0 1 t3eud f gpt =1 t3ud f t3 t3r count t3out t3irq to t2/t4 t3ude
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-9 v2.2, 2004-01 gpt_x1, v2.0 gated timer mode gated timer mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 010 b or 011 b . bit t3m.0 (t3con.3) selects the active level of the gate input. the same options for the input frequency are available in gated timer mode as in timer mode (see section 14.1.5 ). however, the input clock to the timer in this mode is gated by the external input pin t3in (timer t3 external input). to enable this operation, the associated pin t3in must be configured as input, that is, the corresponding direction control bit must contain 0. figure 14-5 block diagram of core timer t3 in gated timer mode if t3m = 010 b , the timer is enabled when t3in shows a low level. a high level at this line stops the timer. if t3m = 011 b , line t3in must have a high level in order to enable the timer. additionally, the timer can be turned on or off by software using bit t3r. the timer will only run if t3r is 1 and the gate is active. it will stop if either t3r is 0 or the gate is inactive. note: a transition of the gate signal at pin t3in does not cause an interrupt request. prescaler gate ctrl. core timer t3 toggle latch mcb05392 bps1 t3i mux up/down 0 1 t3eud f gpt =1 t3ud f t3 t3r count t3out t3irq to t2/t4 t3ude t3in
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-10 v2.2, 2004-01 gpt_x1, v2.0 counter mode counter mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 001 b . in counter mode, timer t3 is clocked by a transition at the external input pin t3in. the event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. bitfield t3i in control register t3con selects the triggering transition (see table 14-2 ). figure 14-6 block diagram of core timer t3 in counter mode for counter mode operation, pin t3in must be configured as input (the respective direction control bit dpx.y must be 0). the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to t3in is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. this information can be found in section 14.1.5 . table 14-2 gpt1 core timer t3 (counter mode) input edge selection t3i triggering edge for counter increment/decrement 0 0 0 none. counter t3 is disabled 0 0 1 positive transition (rising edge) on t3in 0 1 0 negative transition (falling edge) on t3in 0 1 1 any transition (rising or falling edge) on t3in 1 x x reserved. do not use this combination mcb05393 core timer t3 toggle latch mux up/down 0 1 t3eud t3in =1 t3ud t3r count t3out t3irq to t2/t4 t3ude t3i edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-11 v2.2, 2004-01 gpt_x1, v2.0 incremental interface mode incremental interface mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 110 b or 111 b . in incremental interface mode, the two inputs associated with core timer t3 (t3in, t3eud) are used to interface to an incremental encoder. t3 is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input. figure 14-7 block diagram of core timer t3 in incremental interface mode bitfield t3i in control register t3con selects the triggering transitions (see table 14-3 ). the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. so t3 is modified automatically according to the speed and the direction of the incremental encoder and, therefore, its contents always represent the encoder?s current position. the interrupt request (t3irq) generation mode can be selected: in rotation detection mode (t3m = 110 b ), an interrupt request is generated each time the count direction of t3 changes. in edge detection mode (t3m = 111 b ), an interrupt request is generated each time a count edge for t3 is detected. count direction, changes in the count direction, and count requests are monitored by status bits t3rdir, t3chdir, and t3edge in register t3con. mcb05394 count t3eud t3 edge t3 rdir mux 0 1 =1 t3ud t3ude change detect t3ch dir t3m t3m >1 _ phase detect t3r t3in t3i t3irq core timer t3 toggle latch t3out to t2/t4 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user?s manual 14-12 v2.2, 2004-01 gpt_x1, v2.0 the incremental encoder can be connected directly to the XC161 without external interface logic. in a standard system, however, comparators will be employed to convert the encoder?s differential outputs (such as a, a ) to digital signals (such as a). this greatly increases noise immunity. note: the third encoder output t0, which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a reset of timer t3 (for example via pec transfer from zeros). figure 14-8 connection of the encoder to the XC161 for incremental interface operation, the following conditions must be met: bitfield t3m must be 110 b or 111 b . both pins t3in and t3eud must be configured as input, i.e. the respective direction control bits must be 0. bit t3ude must be 1 to enable automatic external direction control. the maximum count frequency allowed in incremental interface mode depends on the selected prescaler value. to ensure that a transition of any input signal is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. this information can be found in section 14.1.5 . table 14-3 core timer t3 (incremental interface mode) input edge selection t3i triggering edge for counter increment/decrement 0 0 0 none. counter t3 stops. 0 0 1 any transition (rising or falling edge) on t3in. 0 1 0 any transition (rising or falling edge) on t3eud. 0 1 1 any transition (rising or falling edge) on any t3 input (t3in or t3eud). 1 x x reserved. do not use this combination. mcs04372 encoder controller a b t0 t3input t3input interrupt a b b t0 t0 a signal conditioning
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-13 v2.2, 2004-01 gpt_x1, v2.0 as in incremental interface mode two input signals with a 90 phase shift are evaluated, their maximum input frequency can be half the maximum count frequency. in incremental interface mode, the count direction is automatically derived from the sequence in which the input signals change, which corresponds to the rotation direction of the connected sensor. table 14-4 summarizes the possible combinations. figure 14-9 and figure 14-10 give examples of t3 ? s operation, visualizing count signal generation and direction control. they also show how input jitter is compensated, which might occur if the sensor rests near to one of its switching points. figure 14-9 evaluation of incremental encoder signals, 2 count inputs table 14-4 gpt1 core timer t3 (incremental interface mode) count direction level on respective other input t3in input t3eud input rising falling rising falling high down up up down low up down down up mct04373 forward jitter backward jitter forward t3in t3eud contents of t3 up down up note: this example shows the timer behaviour assuming that t3 counts upon any transition on input, i.e. t3i = '011 b '.
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-14 v2.2, 2004-01 gpt_x1, v2.0 figure 14-10 evaluation of incremental encoder signals, 1 count input note: timer t3 operating in incremental interface mode automatically provides information on the sensor?s current position. dynamic information (speed, acceleration, deceleration) may be obtained by measuring the incoming signal periods. this is facilitated by an additional special capture mode for timer t5 (see section 14.2.5 ). mct04374 forward jitter backward jitter forward t3in up down up t3eud contents of t3 note: this example shows the timer behaviour assuming that t3 counts upon any transition on input t3in, i.e. t3i = '001 b '.
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-15 v2.2, 2004-01 gpt_x1, v2.0 14.1.3 gpt1 auxiliary timers t2/t4 control auxiliary timers t2 and t4 have exactly the same functionality. they can be configured for timer mode, gated timer mode, counter mode, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer t3. in addition to these 4 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. the start/stop function of the auxiliary timers can be remotely controlled by the t3 run control bit. several timers may thus be controlled synchronously. the current contents of an auxiliary timer are reflected by its count register t2 or t4, respectively. these registers can also be written to by the cpu, for example, to set the initial start value. the individual configurations for timers t2 and t4 are determined by their bitaddressable control registers t2con and t4con, which are organized identically. note that functions which are present in all 3 timers of block gpt1 are controlled in the same bit positions and in the same manner in each of the specific control registers. note: the auxiliary timers have no output toggle latch and no alternate output function. gpt12e_t2con timer 2 control register sfr (ff40 h /a0 h ) reset value: 0000 h 1514131211109876543210 t2 r dir t2 ch dir t2 ed ge t2 ir dis -- t2 rc t2 ude t2 ud t2r t2m t2i rh rwh rwh rw - - rw rw rw rw rw rw gpt12e_t4con timer 4 control register sfr (ff44 h /a2 h ) reset value: 0000 h 1514131211109876543210 t4 r dir t4 ch dir t4 ed ge t4 ir dis -- t4 rc t4 ude t4 ud t4r t4m t4i rh rwh rwh rw - - rw rw rw rw rw rw field bits typ description txrdir 15 rh timer tx rotation direction 0 timer x counts up 1 timer x counts down
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-16 v2.2, 2004-01 gpt_x1, v2.0 txchdir 14 rwh timer tx count direction change this bit is set each time the count direction of timer tx changes. txchdir must be cleared by sw. 0 no change in count direction was detected 1 a change in count direction was detected txedge 13 rwh timer tx edge detection the bit is set each time a count edge is detected. txedge must be cleared by sw. 0 no count edge was detected 1 a count edge was detected txirdis 12 rw timer tx interrupt request disable 0 interrupt generation for txchdir and txedge interrupts in incremental interface mode is enabled 1 interrupt generation for txchdir and txedge interrupts in incremental interface mode is disabled txrc 9rw timer tx remote control 0 timer tx is controlled by its own run bit txr 1 timer tx is controlled by the run bit t3r of core timer 3, not by bit txr txude 8rw timer tx external up/down enable 0 input txeud is disconnected 1 direction influenced by input txeud 1) txud 7rw timer tx up/down control 1) txr 6rw timer tx run bit 0timer tx stops 1timer tx runs note: this bit only controls timer tx if bit txrc = 0. txm [5:3] rw timer tx mode control (basic operating mode) 000 timer mode 001 counter mode 010 gated timer mode with gate active low 011 gated timer mode with gate active high 100 reload mode 101 capture mode 110 incremental interface mode (rotation detect.) 111 incremental interface mode (edge detection) field bits typ description
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-17 v2.2, 2004-01 gpt_x1, v2.0 timer t2/t4 run control each of the auxiliary timers t2 and t4 can be started or stopped by software in two different ways: through the associated timer run bit (t2r or t4r). in this case it is required that the respective control bit txrc = 0. through the core timer ? s run bit (t3r). in this case the respective remote control bit must be set (txrc = 1). the selected run bit is relevant in all operating modes of t2/t4. setting the bit will start the timer, clearing the bit stops the timer. in gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). note: if remote control is selected t3r will start/stop timer t3 and the selected auxiliary timer(s) synchronously. count direction control the count direction of the gpt1 timers (core timer and auxiliary timers) is controlled in the same way, either by software or by the external input pin txeud. please refer to the description in table 14-1 . note: when pin txeud is used as external count direction control input, it must be configured as input (its corresponding direction control bit must be cleared). txi [2:0] rw timer tx input parameter selection depends on the operating mode, see respective sections for encoding: table 14-7 for timer mode and gated timer mode table 14-2 for counter mode table 14-3 for incremental interface mode 1) see table 14-1 for encoding of bits txud and txeud. field bits typ description
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-18 v2.2, 2004-01 gpt_x1, v2.0 14.1.4 gpt1 auxiliary timers t2/t4 operating modes the operation of the auxiliary timers in the basic operating modes is almost identical with the core timer ? s operation, with very few exceptions. additionally, some combined operating modes can be selected. timers t2 and t4 in timer mode timer mode for an auxiliary timer tx is selected by setting its bitfield txm in register txcon to 000 b . figure 14-11 block diagram of an auxiliary timer in timer mode prescaler auxiliary timer tx bps1 txi f gpt f tx count txirq mcb05395 mux up/down 0 1 txeud =1 txud txude mux txrc txr t3r x = 2, 4 0 1
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-19 v2.2, 2004-01 gpt_x1, v2.0 timers t2 and t4 in gated timer mode gated timer mode for an auxiliary timer tx is selected by setting bitfield txm in register txcon to 010 b or 011 b . bit txm.0 (txcon.3) selects the active level of the gate input. note: a transition of the gate signal at line txin does not cause an interrupt request. figure 14-12 block diagram of an auxiliary timer in gated timer mode note: there is no output toggle latch for t2 and t4. start/stop of an auxiliary timer can be controlled locally or remotely. prescaler gate ctrl. auxiliary timer tx bps1 txi f gpt f tx count txirq txm mcb05396 mux up/down 0 1 txeud =1 txud txude mux txrc txr t3r x = 2, 4 0 1 txin
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-20 v2.2, 2004-01 gpt_x1, v2.0 timers t2 and t4 in counter mode counter mode for an auxiliary timer tx is selected by setting bitfield txm in register txcon to 001 b . in counter mode, an auxiliary timer can be clocked either by a transition at its external input line txin, or by a transition of timer t3 ? s toggle latch t3otl. the event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. bitfield txi in control register txcon selects the triggering transition (see table 14-5 ). figure 14-13 block diagram of an auxiliary timer in counter mode note: only state transitions of t3otl which are caused by the overflows/underflows of t3 will trigger the counter function of t2/t4. modifications of t3otl via software will not trigger the counter function of t2/t4. table 14-5 gpt1 auxiliary timer (counter mode) input edge selection t2i/t4i triggering edge for counter increment/decrement x 0 0 none. counter tx is disabled 0 0 1 positive transition (rising edge) on txin 0 1 0 negative transition (falling edge) on txin 0 1 1 any transition (rising or falling edge) on txin 1 0 1 positive transition (rising edge) of t3 toggle latch t3otl 1 1 0 negative transition (falling edge) of t3 toggle latch t3otl 1 1 1 any transition (rising or falling edge) of t3 toggle latch t3otl auxiliary timer tx count txirq mcb05397 mux up/down 0 1 txeud =1 txud txude mux txrc txr t3r x = 2, 4 txi mux txi.2 txin t3 toggle latch 0 1 0 1 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-21 v2.2, 2004-01 gpt_x1, v2.0 for counter operation, pin txin must be configured as input (the respective direction control bit dpx.y must be 0). the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to txin is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. this information can be found in section 14.1.5 . timers t2 and t4 in incremental interface mode incremental interface mode for an auxiliary timer tx is selected by setting bitfield txm in the respective register txcon to 110 b or 111 b . in incremental interface mode, the two inputs associated with an auxiliary timer tx (txin, txeud) are used to interface to an incremental encoder. tx is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input. figure 14-14 block diagram of an auxiliary timer in incremental interface mode the operation of the auxiliary timers t2 and t4 in incremental interface mode and the interrupt generation are the same as described for the core timer t3. the descriptions, figures and tables apply accordingly. mcb05398 count overflow underflow txeud tx edge tx rdir mux 0 1 =1 txud txude change detect & txch dir txm txm & >1 _ phase detect mux txrc txr t3r txin txi txirdis txirq auxiliary timer tx 0 1 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-22 v2.2, 2004-01 gpt_x1, v2.0 timer concatenation using the toggle bit t3otl as a clock source for an auxiliary timer in counter mode concatenates the core timer t3 with the respective auxiliary timer. this concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of t3otl is selected to clock the auxiliary timer. 32-bit timer/counter: if both a positive and a negative transition of t3otl are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer t3. thus, the two timers form a 32-bit timer. 33-bit timer/counter: if either a positive or a negative transition of t3otl is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer t3. this configuration forms a 33-bit timer (16-bit core timer + t3otl + 16-bit auxiliary timer). as long as bit t3otl is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. the count directions of the two concatenated timers are not required to be the same. this offers a wide variety of different configurations. t3, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. figure 14-15 concatenation of core timer t3 and an auxiliary timer mca05399 toggle latch t3out t3irq count t3r core timer t3 operating mode control bps1 txi t3in f gpt auxiliary timer tx txi 0 1 mux txi.2 txin txirq up/down up/down count mux txrc txr t3r 0 1 x = 2, 4 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-23 v2.2, 2004-01 gpt_x1, v2.0 auxiliary timer in reload mode reload mode for an auxiliary timer tx is selected by setting bitfield txm in the respective register txcon to 100 b . in reload mode, the core timer t3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals. the trigger signal is selected the same way as the clock source for counter mode (see table 14-5 ), i.e. a transition of the auxiliary timer ? s input txin or the toggle latch t3otl may trigger the reload. note: when programmed for reload mode, the respective auxiliary timer (t2 or t4) stops independently of its run flag t2r or t4r. the timer input pin txin must be configured as input if it shall trigger a reload operation. figure 14-16 gpt1 auxiliary timer in reload mode upon a trigger signal, t3 is loaded with the contents of the respective timer register (t2 or t4) and the respective interrupt request flag (t2ir or t4ir) is set. note: when a t3otl transition is selected for the trigger signal, the interrupt request flag t3ir will also be set upon a trigger, indicating t3 ? s overflow or underflow. modifications of t3otl via software will not trigger the counter function of t2/t4. to ensure that a transition of the reload input signal applied to txin is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in section 14.1.5 . the reload mode triggered by the t3 toggle latch can be used in a number of different configurations. the following functions can be performed, depending on the selected active transition: mca05400 toggle latch t3out t3irq count t3r core timer t3 operating mode control bps1 txi up/down t3in f gpt auxiliary timer tx txi reload 0 1 mux txi.2 txin txirq x = 2, 4 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-24 v2.2, 2004-01 gpt_x1, v2.0 if both a positive and a negative transition of t3otl are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. this is the standard reload mode (reload on overflow/underflow). if either a positive or a negative transition of t3otl is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow. using this ? single-transition ? mode for both auxiliary timers allows to perform very flexible pulse width modulation (pwm). one of the auxiliary timers is programmed to reload the core timer on a positive transition of t3otl, the other is programmed for a reload on a negative transition of t3otl. with this combination the core timer is alternately reloaded from the two auxiliary timers. figure 14-17 shows an example for the generation of a pwm signal using the ? single- transition ? reload mechanism. t2 defines the high time of the pwm signal (reloaded on positive transitions) and t4 defines the low time of the pwm signal (reloaded on negative transitions). the pwm signal can be output on pin t3out if t3oe = 1. with this method, the high and low time of the pwm signal can be varied in a wide range. note: the output toggle latch t3otl is accessible via software and may be changed, if required, to modify the pwm signal. however, this will not trigger the reloading of t3.
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-25 v2.2, 2004-01 gpt_x1, v2.0 figure 14-17 gpt1 timer reload configuration for pwm generation note: although possible, selecting the same reload trigger event for both auxiliary timers should be avoided. in such a case, both reload registers would try to load the core timer at the same time. if this combination is selected, t2 is disregarded and the contents of t4 is reloaded. mca05401 t2irq auxiliary timer t2 edge select t2i reload 0 1 mux t2i.2 toggle latch t3out t3irq count t3r core timer t3 operating mode control bps1 t3i up/down t3in f gpt t2in auxiliary timer t4 edge select t4i reload 0 1 mux t4i.2 t4in t4irq
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-26 v2.2, 2004-01 gpt_x1, v2.0 auxiliary timer in capture mode capture mode for an auxiliary timer tx is selected by setting bitfield txm in the respective register txcon to 101 b . in capture mode, the contents of the core timer t3 are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer ? s external input pin txin. the capture trigger signal can be a positive, a negative, or both a positive and a negative transition. the two least significant bits of bitfield txi select the active transition (see table 14-5 ). bit 2 of txi is irrelevant for capture mode and must be cleared (txi.2 = 0). note: when programmed for capture mode, the respective auxiliary timer (t2 or t4) stops independently of its run flag t2r or t4r. figure 14-18 gpt1 auxiliary timer in capture mode upon a trigger (selected transition) at the corresponding input pin txin the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag txir will be set. for capture mode operation, the respective timer input pin txin must be configured as input. to ensure that a transition of the capture input signal applied to txin is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in section 14.1.5 . mca05402 toggle latch t3out t3irq count t3r core timer t3 operating mode control bps1 t3i up/down t3in f gpt auxiliary timer tx txi capture txin txirq x = 2, 4 y = 4, 2 to ty edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-27 v2.2, 2004-01 gpt_x1, v2.0 14.1.5 gpt1 clock signal control all actions within the timer block gpt1 are triggered by transitions of its basic clock. this basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield bps1 in register t3con (see figure 14-2 ). the count clock can be generated in two different ways: internal count clock , derived from gpt1 ? s basic clock via a programmable prescaler, is used for (gated) timer mode. external count clock , derived from the timer ? s input pin(s), is used for counter mode. for both ways, the basic clock determines the maximum count frequency and the timer ? s resolution: internal count clock generation in timer mode and gated timer mode, the count clock for each gpt1 timer is derived from the gpt1 basic clock by a programmable prescaler, controlled by bitfield txi in the respective timer ? s control register txcon. the count frequency f tx for a timer tx and its resolution r tx are scaled linearly with lower clock frequencies, as can be seen from the following formula: (14.1) the effective count frequency depends on the common module clock prescaler factor f(bps1) as well as on the individual input prescaler factor 2 . table 14-7 summarizes the resulting overall divider factors for a gpt1 timer that result from these cascaded prescalers. table 14-8 lists a timer ? s parameters (such as count frequency, resolution, and period) resulting from the selected overall prescaler factor and the applied system frequency. note that some numbers may be rounded. table 14-6 basic clock selection for block gpt1 block prescaler 1) 1) please note the non-linear encoding of bitfield bps1. bps1 = 01 b bps1 = 00 b 2) 2) default after reset. bps1 = 11 b bps1 = 10 b prescaling factor for gpt1: f(bps1) f(bps1) = 4 f(bps1) = 8 f(bps1) = 16 f(bps1) = 32 maximum external count frequency f gpt /8 f gpt /16 f gpt /32 f gpt /64 input signal stable time 4 t gpt 8 t gpt 16 t gpt 32 t gpt f tx f gpt f bps1 () 2 -------------------------------------------- - = r tx s [] f bps1 () 2 f gpt mhz [] -------------------------------------------- - =
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-28 v2.2, 2004-01 gpt_x1, v2.0 table 14-7 gpt1 overall prescaler factors for internal count clock individual prescaler for tx common prescaler for module clock 1) 1) please note the non-linear encoding of bitfield bps1. bps1 = 01 b bps1 = 00 b bps1 = 11 b bps1 = 10 b txi = 000 b 481632 txi = 001 b 8163264 txi = 010 b 16 32 64 128 txi = 011 b 32 64 128 256 txi = 100 b 64 128 256 512 txi = 101 b 128 256 512 1024 txi = 110 b 256 512 1024 2048 txi = 111 b 512 1024 2048 4096 table 14-8 gpt1 timer parameters system clock = 10 mhz overall divider factor system clock = 40 mhz frequency resolution period frequency resolution period 2.5 mhz 400 ns 26.21 ms 4 10.0 mhz 100 ns 6.55 ms 1.25 mhz 800 ns 52.43 ms 8 5.0 mhz 200 ns 13.11 ms 625.0 khz 1.6 s 104.9 ms 16 2.5 mhz 400 ns 26.21 ms 312.5 khz 3.2 s 209.7 ms 32 1.25 mhz 800 ns 52.43 ms 156.25 khz 6.4 s 419.4 ms 64 625.0 khz 1.6 s 104.9 ms 78.125 khz 12.8 s 838.9 ms 128 312.5 khz 3.2 s 209.7 ms 39.06 khz 25.6 s 1.678 s 256 156.25 khz 6.4 s 419.4 ms 19.53 khz 51.2 s 3.355 s 512 78.125 khz 12.8 s 838.9 ms 9.77 khz 102.4 s 6.711 s 1024 39.06 khz 25.6 s 1.678 s 4.88 khz 204.8 s13.42 s 2048 19.53 khz 51.2 s 3.355 s 2.44 khz 409.6 s26.84 s 4096 9.77 khz 102.4 s 6.711 s
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-29 v2.2, 2004-01 gpt_x1, v2.0 external count clock input the external input signals of the gpt1 block are sampled with the gpt1 basic clock (see figure 14-2 ). to ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. a signal transition is recognized if two subsequent samples of the input signal represent different levels. therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. thus, the maximum frequency of an input signal must not be higher than half the basic clock. table 14-9 summarizes the resulting requirements for external gpt1 input signals. these limitations are valid for all external input signals to gpt1, including the external count signals in counter mode and incremental interface mode, the gate input signals in gated timer mode, and the external direction signals. 14.1.6 gpt1 timer registers table 14-9 gpt1 external input signal limits system clock = 10 mhz input frequ. factor gpt1 divider bps1 input phase duration system clock = 40 mhz max. input frequency min. level hold time max. input frequency min. level hold time 1.25 mhz 400 ns f gpt /8 01 b 4 t gpt 5.0 mhz 100 ns 625.0 khz 800 ns f gpt /16 00 b 8 t gpt 2.5 mhz 200 ns 312.5 khz 1.6 s f gpt /32 11 b 16 t gpt 1.25 mhz 400 ns 156.25 khz 3.2 s f gpt /64 10 b 32 t gpt 625.0 khz 800 ns gpt12e_tx timer x count register sfr (fe4x h /2y h ) reset value: 0000 h 1514131211109876543210 txvalue rwh table 14-10 gpt1 timer register locations timer register physical address 8-bit address t3 fe42 h 21 h t2 fe40 h 20 h t4 fe44 h 22 h
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-30 v2.2, 2004-01 gpt_x1, v2.0 14.1.7 interrupt control for gpt1 timers when a timer overflows from ffff h to 0000 h (when counting up), or when it underflows from 0000 h to ffff h (when counting down), its interrupt request flag (t2ir, t3ir or t4ir) in register txic will be set. this will cause an interrupt to the respective timer interrupt vector (t2int, t3int or t4int) or trigger a pec service, if the respective interrupt enable bit (t2ie, t3ie or t4ie in register txic) is set. there is an interrupt control register for each of the three timers. note: please refer to the general interrupt control register description for an explanation of the control fields. gpt12e_t2ic timer 2 intr. ctrl. reg. sfr (ff60 h /b0 h ) reset value: - - 00 h 1514131211109876543210 -------gpxt2irt2ie ilvl glvl - - - - - - - rw rwh rw rw rw gpt12e_t3ic timer 3 intr. ctrl. reg. sfr (ff62 h /b1 h ) reset value: - - 00 h 1514131211109876543210 -------gpxt3irt3ie ilvl glvl - - - - - - - rw rwh rw rw rw gpt12e_t4ic timer 4 intr. ctrl. reg. sfr (ff64 h /b2 h ) reset value: - - 00 h 1514131211109876543210 -------gpxt4irt4ie ilvl glvl - - - - - - - rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-31 v2.2, 2004-01 gpt_x1, v2.0 14.2 timer block gpt2 from a programmer ? s point of view, the gpt2 block is represented by a set of sfrs as summarized below. those portions of port and direction registers which are used for alternate functions by the gpt2 block are shaded. figure 14-19 sfrs associated with timer block gpt2 both timers of block gpt2 (t5, t6) can run in one of 3 basic modes: timer mode, gated timer mode, or counter mode. all timers can count up or down. each timer of gpt2 is controlled by a separate control register txcon. each timer has an input pin txin (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. the count direction (up/down) may be programmed via software. an overflow/underflow of core timer t6 is indicated by the output toggle latch t6otl, whose state may be output on the associated pin t6out (alternate pin function). the auxiliary timer t5 may additionally be concatenated with the core timer t6 (through t6otl). the capture/reload register caprel can be used to capture the contents of timer t5, or to reload timer t6. a special mode facilitates the use of register caprel for both functions at the same time. this mode allows frequency multiplication. the capture function is triggered by the input pin capin, or by gpt1 timer ? s t3 input lines t3in and t3eud. the reload function is triggered by an overflow or underflow of timer t6. overflows/underflows of timer t6 may also clock the timers of the capcom units. the current contents of each timer can be read or modified by the cpu by accessing the corresponding timer count registers t5 or t6, located in the non-bitaddressable sfr mc_gpt0102_registers.vsd data registers control registers port registers t5 t5con t5ic t6 t6con t6ic caprel cric odp3 dp3 p3 e p5 p5didis altsel0p3 e interrupt control syscon3 tx gpt2 timer x register caprel gpt2 capture/reload register txcon gpt2 timer x control register txic g pt2 tim er x interrupt ctrl. reg. sysco n3 system ctrl. reg. 3 (per. m gm t.) odp3 port 3 open drain control register dp3 port 3 direction control register p3 port 3 data register altsel0p3 port 3 alternate output select reg. p5 port 5 data register p5didis port 5 digital input disable reg.
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-32 v2.2, 2004-01 gpt_x1, v2.0 space (see section 14.2.7 ). when any of the timer registers is written to by the cpu in the state immediately preceding a timer increment, decrement, reload, or capture operation, the cpu write operation has priority in order to guarantee correct results. the interrupts of gpt2 are controlled through the interrupt control registers txic. these registers are not part of the gpt2 block. the input and output lines of gpt2 are connected to pins of ports p3 and p5. the control registers for the port functions are located in the respective port modules. note: the timing requirements for external input signals can be found in section 14.2.6 , section 14.3 summarizes the module interface signals, including pins. figure 14-20 gpt2 block diagram caprel mode control t5 mode control gpt2 ti mer t5 t6 mode control gpt2 ti mer t6 gpt2 caprel t6otl t5in t3in/ t3eud capin t6in t6out u/d u/d interrupt request (t5ir) interrupt request (crir) interrupt request (t6ir) t6ouf cl ear capture mc_gpt0103_bldiax1.vsd toggle ff clear 2 n : 1 f gpt basic clock t6con.bps2 rel oad
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-33 v2.2, 2004-01 gpt_x1, v2.0 14.2.1 gpt2 core timer t6 control the current contents of the core timer t6 are reflected by its count register t6. this register can also be written to by the cpu, for example, to set the initial start value. the core timer t6 is configured and controlled via its bitaddressable control register t6con. gpt12e_t6con timer 6 control register sfr (ff48 h /a4 h ) reset value: 0000 h 1514131211109876543210 t6 sr t6 clr - bps2 t6 otl t6 oe - t6 ud t6r t6m t6i rw rw - rw rwh rw - rw rw rw rw field bits typ description t6sr 15 rw timer 6 reload mode enable 0 reload from register caprel disabled 1 reload from register caprel enabled t6clr 14 rw timer t6 clear enable bit 0 timer t6 is not cleared on a capture event 1 timer t6 is cleared on a capture event bps2 [12:11] rw gpt2 block prescaler control selects the basic clock for block gpt2 (see also section 14.2.6 ) 00 f gpt /4 01 f gpt /2 10 f gpt /16 11 f gpt /8 t6otl 10 rwh timer t6 overflow toggle latch toggles on each overflow/underflow of t6. can be set or reset by software (see separate description) t6oe 9rw overflow/underflow output enable 0 alternate output function disabled 1 state of t6 toggle latch is output on pin t6out t6ud 7rw timer t6 up/down control 0 timer t6 counts up 1 timer t6 counts down
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-34 v2.2, 2004-01 gpt_x1, v2.0 timer t6 run control the core timer t6 can be started or stopped by software through bit t6r (timer t6 run bit). this bit is relevant in all operating modes of t6. setting bit t6r will start the timer, clearing bit t6r stops the timer. in gated timer mode, the timer will only run if t6r = 1 and the gate is active (high or low, as programmed). note: when bit t5rc in timer control register t5con is set, bit t6r will also control (start and stop) the auxiliary timer t5. count direction control the count direction of the gpt2 timers (core timer and auxiliary timer) can be controlled by software. the count direction can be altered by setting or clearing bit txud. the count direction can be changed regardless of whether or not the timer is running. t6r 6rw timer t6 run bit 0 timer t6 stops 1timer t6 runs t6m [5:3] rw timer t6 mode control (basic operating mode) 000 timer mode 001 counter mode 010 gated timer mode with gate active low 011 gated timer mode with gate active high 100 reserved. do not use this combination. 101 reserved. do not use this combination. 110 reserved. do not use this combination. 111 reserved. do not use this combination. t6i [2:0] rw timer t6 input parameter selection depends on the operating mode, see respective sections for encoding: table 14-15 for timer mode and gated timer mode table 14-11 for counter mode field bits typ description
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-35 v2.2, 2004-01 gpt_x1, v2.0 timer 6 output toggle latch the overflow/underflow signal of timer t6 is connected to a block named ? toggle latch ? , shown in the timer mode diagrams. figure 14-21 illustrates the details of this block. an overflow or underflow of t6 will clock two latches: the first latch represents bit t6otl in control register t6con. the second latch is an internal latch toggled by t6otl ? s output. both latch outputs are connected to the input control block of the auxiliary timer t5. the output level of the shadow latch will match the output level of t6otl, but is delayed by one clock cycle. when the t6otl value changes, this will result in a temporarily different output level from t6otl and the shadow latch, which can trigger the selected count event in t5. when software writes to t6otl, both latches are set or cleared simultaneously. in this case, both signals to the auxiliary timers carry the same level and no edge will be detected. bit t6oe (overflow/underflow output enable) in register t6con enables the state of t6otl to be monitored via an external pin t6out. when t6otl is linked to an external port pin (must be configured as output), t6out can be used to control external hw. if t6oe = 1, pin t6out outputs the state of t6otl. if t6oe = 0, pin t6out outputs a high level (while it selects the timer output signal). as can be seen from figure 14-21 , when latch t6otl is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. therefore, no trigger condition is detected by t5 in this case. figure 14-21 block diagram of the toggle latch logic of core timer t6 note: t6 is also used to clock the timers in the capcom units. for this purpose, there is a direct internal connection between the t6 overflow/underflow line and the capcom timers (signal t6ouf). mc_gpt0106_otl.vsd toggle latch logic txout set/clear (sw ) core timer overflow/ underflow shadow latch 1 0 mux 1 txoe txotl to port logic to aux. timer input logic
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-36 v2.2, 2004-01 gpt_x1, v2.0 14.2.2 gpt2 core timer t6 operating modes timer 6 in timer mode timer mode for the core timer t6 is selected by setting bitfield t6m in register t6con to 000 b . in this mode, t6 is clocked with the module ? s input clock f gpt divided by two programmable prescalers controlled by bitfields bps2 and t6i in register t6con. please see section 14.2.6 for details on the input clock options. figure 14-22 block diagram of core timer t6 in timer mode prescaler core timer t6 toggle latch mcb05403 bps2 t6i up/down f gpt f t6 t6r count t6out t6irq to t5/ caprel t6ud t6ouf
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-37 v2.2, 2004-01 gpt_x1, v2.0 gated timer mode gated timer mode for the core timer t6 is selected by setting bitfield t6m in register t6con to 010 b or 011 b . bit t6m.0 (t6con.3) selects the active level of the gate input. the same options for the input frequency are available in gated timer mode as in timer mode (see section 14.2.6 ). however, the input clock to the timer in this mode is gated by the external input pin t6in (timer t6 external input). to enable this operation, the associated pin t6in must be configured as input (the corresponding direction control bit must contain 0). figure 14-23 block diagram of core timer t6 in gated timer mode if t6m = 010 b , the timer is enabled when t6in shows a low level. a high level at this line stops the timer. if t6m = 011 b , line t6in must have a high level in order to enable the timer. additionally, the timer can be turned on or off by software using bit t6r. the timer will only run if t6r is 1 and the gate is active. it will stop if either t6r is 0 or the gate is inactive. note: a transition of the gate signal at pin t6in does not cause an interrupt request. prescaler gate ctrl. core timer t6 toggle latch mcb05404 bps2 t6i up/down f gpt f t6 t6r count t6out t6irq to t5, caprel clear t6ouf t6ud t6in
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-38 v2.2, 2004-01 gpt_x1, v2.0 counter mode counter mode for the core timer t6 is selected by setting bitfield t6m in register t6con to 001 b . in counter mode, timer t6 is clocked by a transition at the external input pin t6in. the event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. bitfield t6i in control register t6con selects the triggering transition (see table 14-11 ). figure 14-24 block diagram of core timer t6 in counter mode for counter mode operation, pin t6in must be configured as input (the respective direction control bit dpx.y must be 0). the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to t6in is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. this information can be found in section 14.2.6 . table 14-11 gpt2 core timer t6 (counter mode) input edge selection t6i triggering edge for counter increment/decrement 0 0 0 none. counter t6 is disabled 0 0 1 positive transition (rising edge) on t6in 0 1 0 negative transition (falling edge) on t6in 0 1 1 any transition (rising or falling edge) on t6in 1 x x reserved. do not use this combination mcb05405 core timer t6 toggle latch up/down t6ud t6in t6r count t6out t6irq to t5, caprel t6i clear t6ouf edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-39 v2.2, 2004-01 gpt_x1, v2.0 14.2.3 gpt2 auxiliary timer t5 control auxiliary timer t5 can be configured for timer mode, gated timer mode, or counter mode with the same options for the timer frequencies and the count signal as the core timer t6. in addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. the contents of t5 may be captured to register caprel upon an external or an internal trigger. the start/stop function of the auxiliary timers can be remotely controlled by the t6 run control bit. several timers may thus be controlled synchronously. the current contents of the auxiliary timer are reflected by its count register t5. this register can also be written to by the cpu, for example, to set the initial start value. the individual configurations for timer t5 are determined by its bitaddressable control register t5con. some bits in this register also control the function of the caprel register. note that functions which are present in all timers of block gpt2 are controlled in the same bit positions and in the same manner in each of the specific control registers. note: the auxiliary timer has no output toggle latch and no alternate output function. gpt12e_t5con timer 5 control register sfr (ff46 h /a3 h ) reset value: 0000 h 1514131211109876543210 t5 sc t5 clr ci t5 cc ct3 t5 rc - t5 ud t5r t5m t5i rw rw rw rw rw rw - rw rw rw rw field bits typ description t5sc 15 rw timer 5 capture mode enable 0 capture into register caprel disabled 1 capture into register caprel enabled t5clr 14 rw timer t5 clear enable bit 0 timer t5 is not cleared on a capture event 1 timer t5 is cleared on a capture event ci [13:12] rw register caprel capture trigger selection (depending on bit ct3) 00 capture disabled 01 positive transition (rising edge) on capin or any transition on t3in 10 negative transition (falling edge) on capin or any transition on t3eud 11 any transition (rising or falling edge) on capin or any transition on t3in or t3eud
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-40 v2.2, 2004-01 gpt_x1, v2.0 timer t5 run control the auxiliary timer t5 can be started or stopped by software in two different ways: through the associated timer run bit (t5r). in this case it is required that the respective control bit t5rc = 0. through the core timer ? s run bit (t6r). in this case the respective remote control bit must be set (t5rc = 1). the selected run bit is relevant in all operating modes of t5. setting the bit will start the timer, clearing the bit stops the timer. t5cc 11 rw timer t5 capture correction 0 t5 is just captured without any correction 1 t5 is decremented by 1 before being captured ct3 10 rw timer t3 capture trigger enable 0 capture trigger from input line capin 1 capture trigger from t3 input lines t3in and/or t3eud t5rc 9rw timer t5 remote control 0 timer t5 is controlled by its own run bit t5r 1 timer t5 is controlled by the run bit t6r of core timer 6, not by bit t5r t5ud 7rw timer t5 up/down control 0 timer t5 counts up 1 timer t5 counts down t5r 6rw timer t5 run bit 0 timer t5 stops 1timer t5 runs note: this bit only controls timer t5 if bit t5rc = 0. t5m [5:3] rw timer t5 mode control (basic operating mode) 000 timer mode 001 counter mode 010 gated timer mode with gate active low 011 gated timer mode with gate active high 1xx reserved. do not use this combination t5i [2:0] rw timer t5 input parameter selection depends on the operating mode, see respective sections for encoding: table 14-15 for timer mode and gated timer mode table 14-11 for counter mode field bits typ description
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-41 v2.2, 2004-01 gpt_x1, v2.0 in gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). note: if remote control is selected t6r will start/stop timer t6 and the auxiliary timer t5 synchronously. 14.2.4 gpt2 auxiliary timer t5 operating modes the operation of the auxiliary timer in the basic operating modes is almost identical with the core timer ? s operation, with very few exceptions. additionally, some combined operating modes can be selected. timer t5 in timer mode timer mode for the auxiliary timer t5 is selected by setting its bitfield t5m in register t5con to 000 b . figure 14-25 block diagram of auxiliary timer t5 in timer mode prescaler auxiliary timer t5 bps2 t5i f gpt f t5 count t5irq mcb05406 up/down t5ud mux t5rc t5r t6r 0 1 clear
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-42 v2.2, 2004-01 gpt_x1, v2.0 timer t5 in gated timer mode gated timer mode for the auxiliary timer t5 is selected by setting bitfield t5m in register t5con to 010 b or 011 b . bit t5m.0 (t5con.3) selects the active level of the gate input. note: a transition of the gate signal at line t5in does not cause an interrupt request. figure 14-26 block diagram of auxiliary timer t5 in gated timer mode note: there is no output toggle latch for t5. start/stop of the auxiliary timer can be controlled locally or remotely. timer t5 in counter mode counter mode for auxiliary timer t5 is selected by setting bitfield t5m in register t5con to 001 b . in counter mode, the auxiliary timer can be clocked either by a transition at its external input line t5in, or by a transition of timer t6 ? s toggle latch t6otl. the event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. bitfield t5i in control register t5con selects the triggering transition (see table 14-12 ). prescaler gate ctrl. auxiliary timer t5 bps2 t5i t5in f gpt f t5 count t5irq mcb05407 t5ud mux t5rc t5r t6r clear up/down 0 1
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-43 v2.2, 2004-01 gpt_x1, v2.0 figure 14-27 block diagram of auxiliary timer t5 in counter mode note: only state transitions of t6otl which are caused by the overflows/underflows of t6 will trigger the counter function of t5. modifications of t6otl via software will not trigger the counter function of t5. for counter operation, pin t5in must be configured as input (the respective direction control bit dpx.y must be 0). the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to t5in is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. this information can be found in section 14.2.6 . table 14-12 gpt2 auxiliary timer (counter mode) input edge selection t5i triggering edge for counter increment/decrement x 0 0 none. counter t5 is disabled 0 0 1 positive transition (rising edge) on t5in 0 1 0 negative transition (falling edge) on t5in 0 1 1 any transition (rising or falling edge) on t5in 1 0 1 positive transition (rising edge) of t6 toggle latch t6otl 1 1 0 negative transition (falling edge) of t6 toggle latch t6otl 1 1 1 any transition (rising or falling edge) of t6 toggle latch t6otl auxiliary timer t5 count t5irq mcb05408 up/down t5ud mux t5rc t5r t6r t5i mux t5i.2 t5in t6 toggle latch 0 1 clear 0 1 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-44 v2.2, 2004-01 gpt_x1, v2.0 timer concatenation using the toggle bit t6otl as a clock source for the auxiliary timer in counter mode concatenates the core timer t6 with the auxiliary timer t5. this concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of t6otl is selected to clock the auxiliary timer. 32-bit timer/counter: if both a positive and a negative transition of t6otl are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer t6. thus, the two timers form a 32-bit timer. 33-bit timer/counter: if either a positive or a negative transition of t6otl is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer t6. this configuration forms a 33-bit timer (16-bit core timer + t6otl + 16-bit auxiliary timer). as long as bit t6otl is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. the count directions of the two concatenated timers are not required to be the same. this offers a wide variety of different configurations. t6, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. figure 14-28 concatenation of core timer t6 and auxiliary timer t5 mca05409 toggle latch t6out t6irq count t6r core timer t6 operating mode control bps2 t6i clear t6in f gpt auxiliary timer t5 t5i 0 1 mux t5i.2 t5in t5irq up/down clear up/down count mux t5rc t5r t6r 0 1 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-45 v2.2, 2004-01 gpt_x1, v2.0 14.2.5 gpt2 register caprel operating modes the capture/reload register caprel can be used to capture the contents of timer t5, or to reload timer t6. a special mode facilitates the use of register caprel for both functions at the same time. this mode allows frequency multiplication. the capture function is triggered by the input pin capin, or by gpt1 timer ? s t3 input lines t3in and t3eud. the reload function is triggered by an overflow or underflow of timer t6. in addition to the capture function, the capture trigger signal can also be used to clear the contents of timers t5 and t6 individually. the functions of register caprel are controlled via several bit(field)s in the timer control registers t5con and t6con. gpt2 capture/reload register caprel in capture mode capture mode for register caprel is selected by setting bit t5sc in control register t5con (set bitfield ci in register t5con to a non-zero value to select a trigger signal). in capture mode, the contents of the auxiliary timer t5 are latched into register caprel in response to a signal transition at the selected external input pin(s). bit ct3 selects the external input line capin or the input lines t3in and/or t3eud of gpt1 timer t3 as the source for a capture trigger. either a positive, a negative, or both a positive and a negative transition at line capin can be selected to trigger the capture function, or transitions on input t3in or input t3eud or both inputs, t3in and t3eud. the active edge is controlled by bitfield ci in register t5con. table 14-13 summarizes these options. table 14-13 caprel register input edge selection ct3 ci triggering signal/edge for capture mode x 0 0 none. capture mode is disabled. 0 0 1 positive transition (rising edge) on capin. 0 1 0 negative transition (falling edge) on capin. 0 1 1 any transition (rising or falling edge) on capin. 1 0 1 any transition (rising or falling edge) on t3in. 1 1 0 any transition (rising or falling edge) on t3eud. 1 1 1 any transition (rising or falling edge) on t3in or t3eud.
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-46 v2.2, 2004-01 gpt_x1, v2.0 figure 14-29 gpt2 register caprel in capture mode when a selected trigger is detected, the contents of the auxiliary timer t5 are latched into register caprel and the interrupt request line crirq is activated. the same event can optionally clear timer t5 and/or timer t6. this option is enabled by bit t5clr in register t5con and bit t6clr in register t6con, respectively. if txclr = 0 the contents of timer tx is not affected by a capture. if txclr = 1 timer tx is cleared after the current timer t5 value has been latched into register caprel. note: bit t5sc only controls whether or not a capture is performed. if t5sc is cleared the external input pin(s) can still be used to clear timer t5 and/or t6, or as external interrupt input(s). this interrupt is controlled by the caprel interrupt control register cric. when capture triggers t3in or t3eud are enabled (ct3 = 1), register caprel captures the contents of t5 upon transitions of the selected input(s). these values can be used to measure t3 ? s input signals. this is useful, for example, when t3 operates in signal select auxiliary timer t5 t5irq mca05410 up/down clear t5clr t5sc capture caprel register t6clr 0 1 mux ct3 ci capin t3in t3eud count clock t5cc crirq capture correction clear t6 edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-47 v2.2, 2004-01 gpt_x1, v2.0 incremental interface mode, in order to derive dynamic information (speed, acceleration) from the input signals. for capture mode operation, the selected pins capin, t3in, or t3eud must be configured as input. to ensure that a transition of a trigger input signal applied to one of these inputs is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in section 14.2.6 . gpt2 capture/reload register caprel in reload mode reload mode for register caprel is selected by setting bit t6sr in control register t6con. in reload mode, the core timer t6 is reloaded with the contents of register caprel, triggered by an overflow or underflow of t6. this will not activate the interrupt request line crirq associated with the caprel register. however, interrupt request line t6irq will be activated, indicating the overflow/underflow of t6. figure 14-30 gpt2 register caprel in reload mode mca05411 caprel register t6sr core timer t6 reload up/down count clock toggle latch t6out t6irq t6ouf to t5
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-48 v2.2, 2004-01 gpt_x1, v2.0 gpt2 capture/reload register caprel in capture-and-reload mode since the reload function and the capture function of register caprel can be enabled individually by bits t5sc and t6sr, the two functions can be enabled simultaneously by setting both bits. this feature can be used to generate an output frequency that is a multiple of the input frequency. figure 14-31 gpt2 register caprel in capture-and-reload mode this combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, that means, more ? ticks ? within the time between two external events is required. for this purpose, the time between the external events is measured using timer t5 and the caprel register. timer t5 runs in timer mode counting up with a frequency of e.g. f gpt /32. the external events are applied to pin capin. when an external event occurs, auxiliary timer t5 t5irq up/down clear t5sc capture caprel register 0 1 mux ct3 ci capin t3in t3eud count clock t5cc capture correction t5clr crirq mca05412 t6sr core timer t6 clear t6clr reload up/down count clock toggle latch t6out t6irq t6ouf to t5 edge select edge select
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-49 v2.2, 2004-01 gpt_x1, v2.0 the contents of timer t5 are latched into register caprel and timer t5 is cleared (t5clr = 1). thus, register caprel always contains the correct time between two events, measured in timer t5 increments. timer t6, which runs in timer mode counting down with a frequency of e.g. f gpt /4, uses the value in register caprel to perform a reload on underflow. this means, the value in register caprel represents the time between two underflows of timer t6, now measured in timer t6 increments. since (in this example) timer t6 runs 8 times faster than timer t5, it will underflow 8 times within the time between two external events. thus, the underflow signal of timer t6 generates 8 ? ticks ? . upon each underflow, the interrupt request line t6irq will be activated and bit t6otl will be toggled. the state of t6otl may be output on pin t6out. this signal has 8 times more transitions than the signal which is applied to pin capin. note: the underflow signal of timer t6 can furthermore be used to clock one or more of the timers of the capcom units, which gives the user the possibility to set compare events based on a finer resolution than that of the external events. this connection is accomplished via signal t6ouf. capture correction a certain deviation of the output frequency is generated by the fact that timer t5 will count actual time units (e.g. t5 running at 1 mhz will count up to the value 64 h /100 d for a 10 khz input signal), while t6otl will only toggle upon an underflow of t6 (i.e. the transition from 0000 h to ffff h ). in the above mentioned example, t6 would count down from 64 h , so the underflow would occur after 101 timing ticks of t6. the actual output frequency then is 79.2 khz, instead of the expected 80 khz. this deviation can be compensated for by activating the capture correction (t5cc = 1). if capture correction is active, the contents of t5 are decremented by 1 before being captured. the described deviation is eliminated (in the example, t5 would count up to the value 64 h /100 d , but the caprel register will capture the decremented value 63 h /99 d , t6 would count exactly 100 ticks, and the output frequency is 80 khz).
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-50 v2.2, 2004-01 gpt_x1, v2.0 14.2.6 gpt2 clock signal control all actions within the timer block gpt2 are triggered by transitions of its basic clock. this basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield bps2 in register t6con (see figure 14-20 ). the count clock can be generated in two different ways: internal count clock , derived from gpt2 ? s basic clock via a programmable prescaler, is used for (gated) timer mode. external count clock , derived from the timer ? s input pin(s), is used for counter mode. for both ways, the basic clock determines the maximum count frequency and the timer ? s resolution: internal count clock generation in timer mode and gated timer mode, the count clock for each gpt2 timer is derived from the gpt2 basic clock by a programmable prescaler, controlled by bitfield txi in the respective timer ? s control register txcon. the count frequency f tx for a timer tx and its resolution r tx are scaled linearly with lower clock frequencies, as can be seen from the following formula: (14.2) the effective count frequency depends on the common module clock prescaler factor f(bps2) as well as on the individual input prescaler factor 2 . table 14-15 summarizes the resulting overall divider factors for a gpt2 timer that result from these cascaded prescalers. table 14-14 basic clock selection for block gpt2 block prescaler 1) 1) please note the non-linear encoding of bitfield bps2. bps2 = 01 b bps2 = 00 b 2) 2) default after reset. bps2 = 11 b bps2 = 10 b prescaling factor for gpt2: f(bps2) f(bps2) = 2 f(bps2) = 4 f(bps2) = 8 f(bps2) = 16 maximum external count frequency f gpt /4 f gpt /8 f gpt /16 f gpt /32 input signal stable time 2 t gpt 4 t gpt 8 t gpt 16 t gpt f tx f gpt f bps2 () 2 -------------------------------------------- - = r tx s [] f bps2 () 2 f gpt mhz [] -------------------------------------------- - =
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-51 v2.2, 2004-01 gpt_x1, v2.0 table 14-16 lists a timer ? s parameters (such as count frequency, resolution, and period) resulting from the selected overall prescaler factor and the applied system frequency. note that some numbers may be rounded. table 14-15 gpt2 overall prescaler factors for internal count clock individual prescaler for tx common prescaler for module clock 1) bps2 = 01 b bps2 = 00 b bps2 = 11 b bps2 = 10 b txi = 000 b 24816 txi = 001 b 481632 txi = 010 b 8163264 txi = 011 b 16 32 64 128 txi = 100 b 32 64 128 256 txi = 101 b 64 128 256 512 txi = 110 b 128 256 512 1024 txi = 111 b 256 512 1024 2048 1) please note the non-linear encoding of bitfield bps2. table 14-16 gpt2 timer parameters system clock = 10 mhz overall divider factor system clock = 40 mhz frequency resolution period frequency resolution period 5.0 mhz 200 ns 13.11 ms 2 20.0 mhz 50 ns 3.28 ms 2.5 mhz 400 ns 26.21 ms 4 10.0 mhz 100 ns 6.55 ms 1.25 mhz 800 ns 52.43 ms 8 5.0 mhz 200 ns 13.11 ms 625.0 khz 1.6 s 104.9 ms 16 2.5 mhz 400 ns 26.21 ms 312.5 khz 3.2 s 209.7 ms 32 1.25 mhz 800 ns 52.43 ms 156.25 khz 6.4 s 419.4 ms 64 625.0 khz 1.6 s 104.9 ms 78.125 khz 12.8 s 838.9 ms 128 312.5 khz 3.2 s 209.7 ms 39.06 khz 25.6 s 1.678 s 256 156.25 khz 6.4 s 419.4 ms 19.53 khz 51.2 s 3.355 s 512 78.125 khz 12.8 s 838.9 ms 9.77 khz 102.4 s 6.711 s 1024 39.06 khz 25.6 s 1.678 s 4.88 khz 204.8 s13.42 s 2048 19.53 khz 51.2 s 3.355 s
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-52 v2.2, 2004-01 gpt_x1, v2.0 external count clock input the external input signals of the gpt2 block are sampled with the gpt2 basic clock (see figure 14-20 ). to ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. a signal transition is recognized if two subsequent samples of the input signal represent different levels. therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. thus, the maximum frequency of an input signal must not be higher than half the basic clock. table 14-17 summarizes the resulting requirements for external gpt2 input signals. these limitations are valid for all external input signals to gpt2, including the external count signals in counter mode and the gate input signals in gated timer mode. table 14-17 gpt2 external input signal limits system clock = 10 mhz input frequ. factor gpt2 divider bps1 input phase duration system clock = 40 mhz max. input frequency min. level hold time max. input frequency min. level hold time 2.5 mhz 200 ns f gpt /4 01 b 2 t gpt 10.0 mhz 50 ns 1.25 mhz 400 ns f gpt /8 00 b 4 t gpt 5.0 mhz 100 ns 625.0 khz 800 ns f gpt /16 11 b 8 t gpt 2.5 mhz 200 ns 312.5 khz 1.6 s f gpt /32 10 b 16 t gpt 1.25 mhz 400 ns
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-53 v2.2, 2004-01 gpt_x1, v2.0 14.2.7 gpt2 timer registers gpt12e_tx timer x count register sfr (fe4x h /2y h ) reset value: 0000 h 1514131211109876543210 txvalue rwh table 14-18 gpt1 timer register locations timer register physical address 8-bit address t5 fe46 h 23 h t6 fe48 h 24 h gpt12e_caprel capture/reload register sfr (fe4a h /25 h ) reset value: 0000 h 1514131211109876543210 capture/reloadvalue rwh
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-54 v2.2, 2004-01 gpt_x1, v2.0 14.2.8 interrupt control for gpt2 timers and caprel when a timer overflows from ffff h to 0000 h (when counting up), or when it underflows from 0000 h to ffff h (when counting down), its interrupt request flag (t5ir or t6ir) in register txic will be set. whenever a transition according to the selection in bit field ci is detected at pin capin, interrupt request flag crir in register cric is set. setting any request flag will cause an interrupt to the respective timer or caprel interrupt vector (t5int, t6int or crint) or trigger a pec service, if the respective interrupt enable bit (t5ie or t6ie in register txic, crie in register cric) is set. there is an interrupt control register for each of the two timers and for the caprel register. note: please refer to the general interrupt control register description for an explanation of the control fields. gpt12e_t5ic timer 5 intr. ctrl. reg. sfr (ff66 h /b3 h ) reset value: - - 00 h 1514131211109876543210 -------gpxt5irt5ie ilvl glvl - - - - - - - rw rwh rw rw rw gpt12e_t6ic timer 6 intr. ctrl. reg. sfr (ff68 h /b4 h ) reset value: - - 00 h 1514131211109876543210 -------gpxt6irt6ie ilvl glvl - - - - - - - rw rwh rw rw rw gpt12e_cric caprel intr. ctrl. reg. sfr (ff6a h /b5 h ) reset value: - - 00 h 1514131211109876543210 -------gpxcrircrie ilvl glvl - - - - - - - rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) the general purpose timer units user ? s manual 14-55 v2.2, 2004-01 gpt_x1, v2.0 14.3 interfaces of the gpt module besides the described intra-module connections, the timer unit blocks gpt1 and gpt2 are connected to their environment in two basic ways (see figure 14-32 ): internal connections interface the timers with on-chip resources such as clock generation unit, interrupt controller, or other timers. external connections interface the timers with external resources via port pins. figure 14-32 gpt module interfaces port pins to be used for timer input signals must be switched to input, the respective direction control bits must be cleared (dpx.y = 0). port pins to be used for timer output signals must be switched to output, the respective direction control bits must be set (dpx.y = 1). the alternate timer output signal must be selected for these pins via the respective alternate select registers (see chapter 7 ). interrupt nodes to be used for timer interrupt requests must be enabled and programmed to a specific interrupt level. mc_gpt0104_modinterfacex1.vsd system control unit p5.15 t2eud general purpose timer units f gpt p5.14 t4eud p3.7 t2in p3.6 t3in p3.5 t4in p3.4 t3eud p3.3 t3out p5.13 t5in p5.12 t6in p3.2 capin p3.1 t6out t2irq gptdis t3irq t4irq t5irq t6irq crirq t6ouf interrupt control unit capcom units port logic for p3 and p5
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-1 v2.2, 2004-01 rtc_x8, v2.1 15 real time clock the real time clock (rtc) module of the XC161 basically consists of a chain of prescalers and timers. its count clock is derived from the auxiliary oscillator or from the prescaled main oscillator. the rtc serves various purposes: 48-bit timer for long term measurements system clock to determine the current time and date (the rtc ? s structure supports the direct representation of time and date) cyclic time based interrupt (can be generated by any timer of the chain) a number of programming options as well as interrupt request signals adjust the operation of the rtc to the application ? s requirements. the rtc can continue its operation while the XC161 is in a power-saving mode, such that real time date and time information is provided. figure 15-1 sfrs associated with the rtc module the rtc module consists of a chain of 3 divider blocks: a selectable 8:1 divider (on - off) the reloadable 16-bit timer t14 the 32-bit rtc timer block (accessible via rtc_rtch and rtc_rtcl), made of: ? the reloadable 10-bit timer cnt0 ? the reloadable 6-bit timer cnt1 ? the reloadable 6-bit timer cnt2 ? the reloadable 10-bit timer cnt3 all timers count upwards. each of the five timers can generate an interrupt request. all requests are combined to a common node request. note: the rtc registers are not affected by a system reset in order to maintain the correct system time even when intermediate resets are executed. mca04463_xc.vsd rtc_con rtc_t14rel rtc_t14 rtc_isnc control registers data registers counter registers interrupt control rtc_t14 timer t14 count register rtc_t14rel timer t14 reload register rtc_rtch/l rtc count registers, high/low rtc_relh/l rtc reload reg., high/low rtc_ic e ee rtc_rtch e rtc_rtcl e e rtc_con real time clock control register syscon0 general system control register syscon3 power management control reg. rtc_isnc interrupt subnode control register rtc_ic rtc interrupt control register e rtc_relh e rtc_rell e syscon3 e syscon0 e
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-2 v2.2, 2004-01 rtc_x8, v2.1 15.1 defining the rtc time base the timer chain of the rtc is clocked with the count clock signal f rtc which is derived from the auxiliary oscillator or from the prescaled main oscillator (see figure 15-2 and figure 15-3 ). optionally prescaled by a factor of 8, this is the basic rtc clock. depending on the operating mode, timer t14 may provide the count increments used by the application and thus determine the input frequency of the rtc timer, that is, the rtc time base (see also table 15-3 ). the rtc is also supplied with the system clock f sys of the XC161. this clock signal is used to control the rtc ? s logic blocks and its bus interface. to synchronize properly to the count clock, the system clock must run at least four times faster than the count clock, this means f sys 4 f cnt . figure 15-2 rtc clock supply block diagram for an example, table 15-1 lists the interrupt period range and the t14 reload values (for a time base of 1 s and 1 ms): note: select one value from the reload value pairs, depending if the 8:1 prescaler is disabled/enabled. table 15-1 rtc time base examples oscillator frequency t14 intr. period reload value a reload value b min. max. t14rel base t14rel base 32.768 khz 30.52 s 16.0 s 8000 h /f000 h 1.000 s ffdf h / fffc h 1.007 ms/ 0.977 ms clock generation unit mcb05413 8:1 mux pre f cnt rtc count clock 1 0 f sys 32:1 >1 f osca f oscm aux. osc main osc f rtca f rtcm mux f rtc refclk run mux rtc module clock rtccm syscon0.14 1 0 sync mode async mode
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-3 v2.2, 2004-01 rtc_x8, v2.1 asynchronous operation when the system clock frequency becomes lower than 4 f cnt proper synchronization is not possible and count events may be missed. when the XC161 enters e.g. sleep mode the system clock stops completely and the rtc would stop counting. in these cases the rtc can be switched to asynchronous mode (by setting bit rtccm in register syscon0). in this mode the count registers are directly controlled by the count clock independent of the system clock (hence the name). asynchronous operation ensures correct time-keeping even during sleep mode or powerdown mode. however, as no synchronization between the count registers and the bus interface can be maintained in asynchronous mode, the rtc registers cannot be written. read accesses may interfere with count events and, therefore, must be verified (e.g. by reading the same value with three consecutive read accesses). note: the access restrictions in asynchronous mode are only meaningful if the system clock is not switched off, of course. switching clocking modes the clocking mode of the rtc (synchronous or asynchronous) is selected via bit rtccm in register syscon0. after reset, the rtc operates in synchronous mode (rtccm = 0) with the 8:1 prescaler enabled. the selected clocking mode also affects the access to rtc registers. bit accpos in register rtc_con indicates if full register access is possible (accpos = 1, default after reset) or not (accpos = 0). this also indicates the current clocking mode. attention: software should poll bit accpos to determine the proper transition to the intended clocking mode. after switching to asynchronous mode (rtccm = 1), bit accpos = 0 indicates proper operation in asynchronous mode. in this case the system clock can be stopped or reduced. after switching to synchronous mode, (rtccm = 0), bit accpos = 1 indicates proper operation in synchronous mode. in this case the rtc registers can again be accessed properly (read and write). note: the rtc might lose a counting event (edge of f cnt ) when switching from synchronous mode to asynchronous mode while the 8:1 prescaler is disabled. for these applications it is, therefore, recommended to set up the rtc with the 8:1 prescaler enabled.
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-4 v2.2, 2004-01 rtc_x8, v2.1 increased rtc accuracy through software correction the accuracy of the XC161 ? s rtc is determined by the oscillator frequency and by the respective prescaling factor (excluding or including t14 and the 8:1 prescaler). the accuracy limit generated by the prescaler is due to the quantization of a binary counter (where the average is zero), while the accuracy limit generated by the oscillator frequency is due to the difference between the ideal and real frequencies (and therefore accumulates over time). this effect is predictable and can be compensated. the total accuracy of the rtc can be further increased via software for specific applications that demand a high time accuracy. the key to the improved accuracy is knowledge of the exact oscillator frequency. the relation of this frequency to the expected ideal frequency is a measure of the rtc ? s deviation. the number of cycles, n, after which this deviation causes an error of 1 cycle can be easily computed. so, the only action is to correct the count by 1 after each series of n cycles. the correction may be made cyclically, for instance, within an interrupt service routine, or by evaluating a formula when the rtc registers are read (for this the respective ? last ? rtc value must be available somewhere). note: for the majority of applications, however, the standard accuracy provided by the rtc ? s structure will be more than sufficient. adjusting the current rtc value would require reading and then writing the complete 48-bit value. this can only be accomplished by three successive accesses each. to avoid the hassle of reading/writing multi-word values, the rtc incorporates a correction option to simply add or suppress one count pulse. this is done by setting bit t14inc or t14dec, respectively, in register rtc_con. this will add an extra count pulse (t14inc) upon the next count event, or suppress the next count event (t14dec). the respective bit remains set until its associated action has been performed and is automatically cleared by hardware after this event. note: setting both bits, t14inc and t14dec, at the same time will have no effect on the count values.
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-5 v2.2, 2004-01 rtc_x8, v2.1 15.2 rtc run control if the rtc shall operate bit run in register rtc_con must be set (default after reset). bit run can be cleared, for example, to exclude certain operation phases from time keeping. the rtc can be completely disabled by setting the corresponding bit rtcdis in register syscon3. note: a valid count clock is required for proper rtc operation, of course. a reset for the rtc is triggered via software by setting bit rtcrst in register syscon0. in this case all rtc registers are set to their initial values and bit rtcrst is cleared automatically. a normal system reset does not affect the rtc registers and its operation (rtc_ic will be reset, however). the initialization software must ensure the proper rtc operating mode. the rtc control register rtc_con selects the basic operation of the rtc module. rtc_con control register esfr (f110 h /88 h ) reset value: 8003 h 1514131211109876543210 acc pos ---------- ref clk t14 inc t14 dec pre run rh----------rw rwh rwh rw rw field bits type description accpos 15 rh rtc register access possible 0 no write access is possible, only asynchronous reads 1 registers can be read and written refclk 4rw reference clock source 0 the rtc count clock is derived from the auxiliary oscillator ( f osca ) 1 the rtc count clock is derived from the main oscillator ( f oscm /32) t14inc 3rwh increment timer t14 value setting this bit to 1 adds one count pulse upon the next count event, thus incrementing t14. this bit is cleared by hardware after incrementation. t14dec 2rwh decrement timer t14 value setting this bit to 1 suppresses the next count event, thus decrementing t14. this bit is cleared by hardware after decrementation.
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-6 v2.2, 2004-01 rtc_x8, v2.1 pre 1rw rtc input source prescaler enable 0 prescaler disabled, t14 clocked with f rtc 1 prescaler enabled, t14 clocked with f rtc /8 run 0rw rtc run bit 0 rtc stopped 1rtc runs field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-7 v2.2, 2004-01 rtc_x8, v2.1 15.3 rtc operating modes the rtc can be configured for several operating modes according to the purpose it is meant to serve. these operating modes are configured by selecting appropriate reload values and interrupt signals. figure 15-3 rtc block diagram rtc register access the actual value of the rtc is indicated by the three registers t14, rtcl, and rtch. as these registers are concatenated to build the rtc counter chain, internal overflows occur while the rtc is running. when reading or writing the rtc value, such internal overflows must be taken into account to avoid reading/writing corrupted values. care must be taken, when reading the timer(s), as this requires up to three read accesses to the different registers with an inherent time delay between the accesses. an overflow from t14 to rtcl and/or from rtcl to rtch might occur between the accesses, which needs to be taken into account appropriately. for example, reading/writing 0000 h to rtch and then accessing rtcl could produce a corrupted value as rtcl may overflow before it can be accessed. in this case, rtch would be 0001 h . the same precautions must be taken for t14 and t14rel. mcb04805_xc.vsd t14rel t14 t14-register cnt-register rel-register 10 bits 6 bits 6 bits 10 bits 10 bits 6 bits 6 bits 10 bits interrupt sub node cnt in t0 cnt int1 cnt in t2 cnt int3 rtcint 1 0 8 run pre f rtc mux f cnt
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-8 v2.2, 2004-01 rtc_x8, v2.1 timer t14 and its reload register are accessed via dedicated locations. the four rtc counters cnt3 ? cnt0 are accessed via the two 16-bit rtc timer registers, rtch and rtcl. the associated four reload values rel3 ? rel0 are accessed via the two 16-bit rtc reload registers, relh and rell. table 15-2 register locations for timer t14 register name long/short address reset value notes rtc_t14 f0d2 h /69 h 0000 h 16-bit timer, can be used as prescaler for the rtc block rtc_t14rel f0d0 h /68 h 0000 h timer t14 reload register rtc_rtch rtc timer high register esfr (f0d6 h /6b h ) reset value: 0000 h 1514131211109876543210 cnt3 cnt2 rwh rwh rtc_rtcl rtc timer low register esfr (f0d4 h /6a h ) reset value: 0000 h 1514131211109876543210 cnt1 cnt0 rwh rwh field bits type description cntx (x = 3 ? 0) [15:6] [5:0] [15:10] [9:0] rwh rtc timer count section cntx an overflow of this bitfield triggers a count pulse to the next count section cntx+1 (except for cnt3) followed by a reload of cntx from bitfield relx. in addition, an interrupt request is triggered.
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-9 v2.2, 2004-01 rtc_x8, v2.1 note: the registers of the rtc receive their reset values only upon a specific rtc reset. this reset is not triggered upon a system reset, but via software. rtc_relh rtc reload high register esfr (f0ce h /67 h ) reset value: 0000 h 1514131211109876543210 rel3 rel2 rw rw rtc_rell rtc reload low register esfr (f0cc h /66 h ) reset value: 0000 h 1514131211109876543210 rel1 rel0 rw rw field bits type description relx (x = 3 ? 0) [15:6] [5:0] [15:10] [9:0] rw rtc reload value relx this bitfield is copied to bitfield cntx upon an overflow of count section cntx.
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-10 v2.2, 2004-01 rtc_x8, v2.1 15.3.1 48-bit timer operation the concatenation of timers t14 and count0 ? count3 can be regarded as a 48-bit timer which is clocked with the rtc input frequency, optionally divided by the prescaler. the reload registers t14rel, rell, and relh must be cleared to produce a true binary 48-bit timer. however, any other reload value may be used. reload values other than zero must be used carefully, due to the individual sections of the rtc timer with their own individual overflows and reload values. the maximum usable timespan is 2 48 ( 10 14 ) t14 input clocks (assuming no prescaler), which would equal more than 200 years at an oscillator frequency of 32 khz. 15.3.2 system clock operation a real time system clock can be maintained that keeps on running also during power saving modes (optionally) and indicates the current time and date. this is possible because the rtc module is not affected by a system reset 1) . the resolution for this clock information is determined by the input clock of timer t14. by selecting appropriate reload values each cascaded timer can represent directly a part of the current time and/or date. due to its width, t14 can adjust the rtc to the intended range of operation (time or date). the maximum usable timespan is achieved when t14rel is loaded with 0000 h and so t14 divides by 2 16 . system clock example the rtc count clock is f osca (8:1 prescaler off). by selecting appropriate reload values the rtc timers directly indicate the current time (see figure 15-4 and table 15-3 ). figure 15-4 rtc configuration example note: this setup can generate an interrupt request every millisecond, every second, every minute, every hour, or every day. 1) after a power on reset, however, the rtc registers are undefined. mca05414 hours rel3 3e8 h cnt3 minutes rel2 04 h cnt2 seconds rel1 04 h cnt1 1/1000 seconds rel0 018 h cnt0 prescaler t14rel ffdf h t14 f cnt = 32.768 khz
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-11 v2.2, 2004-01 rtc_x8, v2.1 each timer in the chain divides the clock by (2 - ) : 1, as the timers count up. table 15-3 shows the reload values which must be chosen for a specific scenario (i.e. operating mode of the rtc). 15.3.3 cyclic interrupt generation the rtc module can generate an interrupt request whenever one of the timers overflows and is reloaded. this interrupt request may be used, for example, to provide a system time tick independent of the cpu frequency without loading the general purpose timers, or to wake up regularly from sleep mode. the interrupt cycle time can be adjusted by choosing appropriate reload values and by enabling the appropriate interrupt request. in this mode, the other operating modes can be combined. for example, a reload value of t14rel = f9c0 h (2 16 - 1600) generates a t14 interrupt request every 50 ms to wake- up the system regularly. still the subsequent timers can be configured to represent the time or build a binary counter, however with a different time base. table 15-3 reload value scenarios rel3 rel2 rel1 rel0 t14rel time of day ( figure 15-4 ) formula 2 10 - 24 2 6 - 60 2 6 - 60 2 10 - 1000 2 16 - 33 rel. value 3e8 h 04 h 04 h 018 h ffdf h function h m s 1/1000 s prescaler intr. period day hour minute second millisec. 1) 1) t14 errors in the first example (ms) can be compensated either by choosing an adapted value for rel0, or by using software correction. day of the week formula 2 10 - 7 2 6 - 24 2 6 - 60 2 10 - 60 2 16 - 32768 rel. value 3f9 h 28 h 04 h 3c4 h 8000 h function day h m s prescaler intr. period week day hour minute second
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-12 v2.2, 2004-01 rtc_x8, v2.1 15.4 rtc interrupt generation the overflow signals of each timer of the rtc timer chain can generate an interrupt request. the rtc ? s interrupt subnode control register isnc combines these requests to activate the common rtc interrupt request line rtc_irq. each timer overflow sets its associated request flag in register isnc. individual enable bits for each request flag determine whether this request also activates the common interrupt line. the enabled requests are ored together on this line (see figure 15-5 ). the interrupt handler can determine the source of an interrupt request via the specific request flags and must clear them after appropriate processing (not cleared by hardware). the common node request bit is automatically cleared when the interrupt handler is vectored to. note: if only one source is enabled, no additional software check is required, of course. both the individual request and the common interrupt node must be enabled. figure 15-5 interrupt block diagram mcb05415 >1 _ interrupt request rtc_irq & & & & & register rtc_isnc cnt3 ir cnt3 ie set sw clear cnt2 ir cnt2 ie set sw clear cnt1 ir cnt1 ie set sw clear cnt0 ir cnt0 ie set sw clear t14 ir t14 ie set sw clear cnt3 overflow cnt2 overflow cnt1 overflow cnt0 overflow t14 overflow
XC161 derivatives peripheral units (vol. 2 of 2) real time clock user ? s manual 15-13 v2.2, 2004-01 rtc_x8, v2.1 note: the interrupt request flags in register isnc must be cleared by software. they are not cleared automatically when the service routine is entered. note: please refer to the general interrupt control register description for an explanation of the control fields. register rtc_ic is not part of the rtc module and is reset with any system reset. rtc_isnc interrupt subnode ctrl. reg. esfr (f10c h /86 h ) reset value: 0000 h 1514131211109876543210 ------ cnt 3ir cnt 3ie cnt 2ir cnt 2ie cnt 1ir cnt 1ie cnt 0ir cnt 0ie t14 ir t14 ie ------ rwh rw rwh rw rwh rw rwh rw rwh rw field bits type description cntxir (x = 3 ? 0) 9, 7, 5, 3 rwh section cntx interrupt request flag 0 no request pending 1 this source has raised an interrupt request cntxie (x = 3 ? 0) 8, 6, 4, 2 rw section cntx interrupt enable control bit 0 interrupt request is disabled 1 interrupt request is enabled t14ir 1rwh t14 overflow interrupt request flag 0 no request pending 1 this source has raised an interrupt request t14ie 0rw t14 overflow interrupt enable control bit 0 interrupt request is disabled 1 interrupt request is enabled rtc_ic rtc interrupt ctrl. reg. esfr (f1a0 h /d0 h ) reset value: 0000 h 1514131211109876543210 -------gpx rtc ir rtc ie ilvl glvl -------rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-1 v2.2, 2004-01 adc_x1, v2.1 16 the analog/digital converter the XC161 provides an analog/digital converter with 8-bit or 10-bit resolution and a sample & hold circuit on-chip. an input multiplexer selects between up to 12 analog input channels (alternate functions of port 5) either via software (fixed channel modes) or automatically (auto scan modes). to fulfill most requirements of embedded control applications the adc supports the following conversion modes: fixed channel single conversion produces just one result from the selected channel fixed channel continuous conversion repeatedly converts the selected channel auto scan single conversion produces one result from each of a selected group of channels auto scan continuous conversion repeatedly converts the selected group of channels wait for addat read mode start a conversion automatically when the previous result was read channel injection mode start a conversion when a hardware trigger occurs, can insert the conversion of a specific channel into a group conversion (auto scan) a set of sfrs and port pins provide access to control functions and results of the adc. the enhanced-mode registers provide more detailed control functions for the adc. figure 16-1 sfrs and port pins associated with the a/d converter mc_adc0100_registers.vsd data registers control registers system registers adc_dat adc_con adc_cic adc_eic p5 p5didis e interrupt control syscon3 compatibility mode: adc_con adc control register adc_con1 adc control register 1 enhanced mode: adc_ctr0 adc control register 0 adc_ctr2 adc control register 2 adc_ctr2in adc control injection register adc_dat adc result register adc_dat2 adc injection result register adc_cic adc end-of-conversion intr. reg. adc_eic adc conversion-error intr. reg. p5 port 5 analog input port (an15...an12, an7...an0) p5didis port 5 digital input disable reg. adc_dat2 e adc_con1 adc_ctr0 adc_ctr2 adc_ctr2in
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-2 v2.2, 2004-01 adc_x1, v2.1 the external analog reference voltages v aref and v agnd are fixed. the separate supply for the adc reduces the interference with other digital signals. the reference voltages must be stable during the reset calibration phase and during an entire conversion, to achieve a maximum of accuracy. the sample time as well as the conversion time is programmable, so the adc can be adjusted to the internal resistances of the analog sources and/or the analog reference voltage supply (you may also want to refer to application note ap2428). figure 16-2 analog/digital converter block diagram the adc is implemented as a capacitive network using successive approximation conversion. a conversion consists of 3 phases. during the sample phase, the capacitive network is connected to the selected analog input and is charged or discharged to the voltage of the analog signal. during the actual conversion phase, the network is disconnected from the analog input and is repeatedly charged or discharged via v aref during the steps of successive approximation. after the (optional) post-calibration phase (to adjust the network to changing conditions such as temperature) the result is written to the result register and an interrupt request is generated. there are two sets of control, data, and status registers, one set for compatibility mode and one set for enhanced mode. only one of these register sets may be active at a given time. as most of the bits and bitfields of the registers of the two sets control the same functionality or control the functionality in a very similar way, the following description is organized according to the functionality, not according to the two register sets. mcb05416 conversion control adc_cirq sample & hold 8/10-bit capacitive network conversion adc_eirq mux con1 ctr2in con ctr2 ctr0 dat dat2 mux an0 an7 an12 an15 requests injection
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-3 v2.2, 2004-01 adc_x1, v2.1 16.1 mode selection the analog input channels an15 ? an12, an7 ? an0 are alternate functions of port 5 which is an input-only port. the port 5 lines may either be used as analog or digital inputs. for pins that shall be used as analog inputs it is recommended to disable the digital input stage via register p5didis. this avoids undesired cross currents and switching noise while the (analog) input signal level is between v il and v ih . the functions of the a/d converter are controlled by two sets of bit-addressable control registers. in compatibility mode, registers adc_con and adc_con1 are used, in enhanced mode, registers adc_ctr0, adc_ctr2, and adc_ctr2in are used. their bitfields specify the analog channel to be acted upon, the conversion mode, and also reflect the status of the converter. 16.1.1 compatibility mode in compatibility mode (md = 0), registers adc_con and adc_con1 select the basic functions. the register layout is compatible with previous versions of the adc module, while providing limited options. adc_con adc control register sfr (ffa0 h /d0 h ) reset value: 0000 h 1514131211109876543210 adctc adstc ad crq ad cin ad wr ad bsy ad st - adm adch rw rw rwh rw rw rwh rwh - rw rw field bits type function adctc [15:14] rw adc conversion time control (defines the adc basic conversion clock f bc ) 00 f bc = f adc /4 01 f bc = f adc /2 10 f bc = f adc /16 11 f bc = f adc /8 adstc [13:12] rw adc sample time control (defines the adc sample time in a certain range) 00 t bc 8 01 t bc 16 10 t bc 32 11 t bc 64 adcrq 11 rwh adc channel injection request flag adcin 10 rw adc channel injection enable
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-4 v2.2, 2004-01 adc_x1, v2.1 adwr 9rw adc wait for read control adbsy 8rh adc busy flag 0 adc is idle 1 a conversion is active adst 7rwh adc start bit 0 stop a running conversion 1 start conversion(s) adm [5:4] rw adc mode selection 00 fixed channel single conversion 01 fixed channel continuous conversion 10 auto scan single conversion 11 auto scan continuous conversion adch [3:0] rw adc analog channel input selection selects the (first) adc channel which is to be converted. adc_con1 adc control register 1 sfr (ffa6 h /d3 h ) reset value: 0000 h 1514131211109876543210 icst sam ple cal res adctc adstc rw rh rh rw rw rw field bits type description icst 15 rw improved conversion and sample timing selects the active timing control bitfields 0 standard conversion and sample time control, 2-bit fields in adc_con (default after reset) 1 improved conversion and sample time control, 6-bit fields in adc_con1 sample 14 rh sample phase status flag 0 a/d converter is not in sampling 1 a/d converter is currently in the sample phase cal 13 rh reset calibration phase status flag 0 a/d converter is not in calibration phase 1 a/d converter is in calibration phase field bits type function
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-5 v2.2, 2004-01 adc_x1, v2.1 note: the limit values for f bc (see data sheet) must not be exceeded when selecting adctc and f adc . 16.1.2 enhanced mode in enhanced mode (md = 1), registers adc_ctr0, adc_ctr2, and adc_ctr2in select the basic functions. the register layout differs from the compatibility-mode layout, but this mode provides more options. conversion timing is selected via registers adc_ctr2(in), where adc_ctr2 controls standard conversions and adc_ctr2in controls injected conversions. res 12 rw conversion resolution control 0 10-bit resolution (default after reset) 1 8-bit resolution adctc [11:6] rw adc conversion time control defines the adc basic conversion clock: f bc = f adc / ( + 1) adstc [5:0] rw adc sample time control defines the adc sample time: t s = t bc 4 ( + 1) adc_ctr0 adc control register 0 sfr (ffbe h /df h ) reset value: 1000 h 1514131211109876543210 md sam ple adcts ad crq ad cin ad wr ad bsy ad st adm cal off adch rw rh rw rwh rw rw rh rwh rw rw rw field bits type description md 15 rw mode control 0 compatibility mode 1 enhanced mode note: any modification of control bit md is forbidden while a conversion is currently running. user software must take care. sample 14 rh sample phase status flag 0 a/d converter is not in sample phase 1 a/d converter in sample phase field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-6 v2.2, 2004-01 adc_x1, v2.1 adcts [13:12] rw channel injection trigger input select 00 channel injection trigger input disabled 01 trigger input capcom selected 10 reserved 11 reserved note: reset value of bitfield adcts is 01 b for compatibility purposes. adcrq 11 rwh channel injection request flag adcin 10 rw channel injection enable control adwr 9rw wait for read control adbsy 8rh busy flag 0 adc is idle 1 a conversion is active adst 7rwh adc start/stop control 0 stop a running conversion 1 start conversion(s) adm [6:5] rw mode selection control 00 fixed channel single conversion 01 fixed channel continuous conversion 10 auto scan single conversion 11 auto scan continuous conversion caloff 4rw calibration disable control 0 calibration cycles are executed 1 calibration is disabled (off) note: this control bit is active in both compatibility and enhanced mode. adch [3:0] rw analog input channel selection selects the (first) adc channel which is to be converted field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-7 v2.2, 2004-01 adc_x1, v2.1 note: the limit values for f bc (see data sheet) must not be exceeded when selecting adctc and f adc . adc_ctr2 adc control register 2 esfr (f09c h /4e h ) reset value: 0000 h 1514131211109876543210 - res adctc adstc -rw rw rw adc_ctr2in injection control register 2 esfr (f09e h /4f h ) reset value: 0000 h 1514131211109876543210 - res adctc adstc rrw rw rw field bits type description res [13:12] rw converter resolution control 00 10-bit resolution (default after reset) 01 8-bit resolution 1x reserved adctc [11:6] rw adc conversion time control defines the adc basic conversion clock: f bc = f adc / ( + 1) adstc [5:0] rw adc sample time control defines the adc sample time: t s = t bc 4 ( + 1)
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-8 v2.2, 2004-01 adc_x1, v2.1 16.2 adc operation channel selection, adch bitfield adch controls the input channel multiplexer logic. in the single channel modes, it specifies the analog input channel which is to be converted. in the auto scan modes, it specifies the highest channel number to be converted in the auto scan round. adch may be changed while a conversion is in progress. the new value will go into effect after the current conversion is finished in the fixed channel modes, or after the current conversion round is finished in the auto scan modes. adc flags, adbsy, sample the adc busy status flag is set when the adc is started (by setting adst) and remains set as long as the adc performs conversions or calibration cycles. adbsy is cleared when the adc is idle, meaning there are no conversion or calibration operations in progress. bit sample is set during the sample phase. adc start/stop control, adst bit adst is used to start or to stop the adc. a single conversion or a conversion sequence is started by setting bit adst. the busy flag adbsy will be set and the converter then selects and samples the input channel, which is specified by the channel selection field adch. the sampled level will then be held internally during the conversion. when the conversion of this channel is complete, the result together with the number of the converted channel is transferred into the result register and the interrupt request is generated. the conversion result is placed into bitfield adres. adst remains set until cleared either by hardware or by software. hardware clears the bit dependent on the conversion mode: in fixed channel single conversion mode, adst is cleared after the conversion of the specified channel is finished. in auto scan single conversion mode, adst is cleared after the conversion of channel 0 is finished. note: in the continuous conversion modes, adst is never cleared by hardware. stopping the adc via software is performed by clearing bit adst. the reaction of the adc depends on the conversion mode: in fixed channel single conversion mode, the adc finishes the conversion and then stops. there is no difference to the operation if adst was not cleared by software. in fixed channel continuous conversion mode, the adc finishes the current conversion and then stops. this is the usual way to terminate this conversion mode.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-9 v2.2, 2004-01 adc_x1, v2.1 in auto scan single conversion mode, the adc continues the auto scan round until the conversion of channel 0 is finished, then it stops. there is no difference to the operation if adst was not cleared by software. in auto scan continuous conversion mode, the adc continues the auto scan round until the conversion of channel 0 is finished, then it stops. this is the usual way to terminate this conversion mode. a restart of the adc can be performed by clearing and then setting bit adst. this sequence will abort the current conversion and restart the adc with the new parameters given in the control registers. conversion mode selection, adm bitfield adm selects the conversion mode of the a/d converter, as listed in table 16-1 . while a conversion is in progress, the mode selection field adm and the channel selection field adch may be changed. adm will be evaluated after the current conversion. adch will be evaluated after the current conversion (fixed channel modes) or after the current conversion sequence (auto scan modes). conversion resolution control, res the adc can produce either a 10-bit result (res = 0) or an 8-bit result (res = 1). depending on the application ? s needs a higher conversion speed (an 8-bit conversion requires less conversion time) or a higher resolution can be chosen. table 16-1 a/d converter conversion mode adm description 00 fixed channel single conversion 01 fixed channel continuous conversion 10 auto scan single conversion 11 auto scan continuous conversion
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-10 v2.2, 2004-01 adc_x1, v2.1 conversion result the result of a conversion is stored in the result register adc_dat, or in register adc_dat2 for an injected conversion. the position of the result depends on the basic operating mode (compatibility or enhanced) and on the selected resolution (8-bit or 10-bit). note: bitfield chnr of register adc_dat is loaded by the adc to indicate, which channel the result refers to. bitfield chnr of register adc_dat2 is loaded by the cpu to select the analog channel, which is to be injected. adc_dat adc result register sfr (fea0 h /50 h ) reset value: 0000 h 1514131211109876543210 chnr adres rwh rwh adc_dat2 adc chan. inj. result reg. esfr (f0a0 h /50 h ) reset value: 0000 h 1514131211109876543210 chnr adres rw rwh field bits type function chnr [15:12] rw[h] channel number (identifies the converted analog channel) adres [11:0] rwh a/d conversion result the digital result of the most recent conversion. in compatibility mode, the result is placed as follows: 8-bit: adres[9:2] 10-bit: adres[9:0] in enhanced mode, the result is placed as follows: 8-bit: adres[11:4] 10-bit: adres[11:2] note: unused bits of adres are always set to 0.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-11 v2.2, 2004-01 adc_x1, v2.1 16.2.1 fixed channel conversion modes these modes are selected by programming the mode selection bitfield adm to 00 b (single conversion) or to 01 b (continuous conversion). after starting the converter through bit adst the busy flag adbsy will be set and the channel specified in bitfield adch will be converted. after the conversion is complete, the interrupt request flag adcir will be set. in single conversion mode the converter will automatically stop and reset bits adbsy and adst. in continuous conversion mode the converter will automatically start a new conversion of the channel specified in adch. adcir will be set after each completed conversion. when bit adst is reset by software, while a conversion is in progress, the converter will complete the current conversion and then stop and reset bit adbsy.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-12 v2.2, 2004-01 adc_x1, v2.1 16.2.2 auto scan conversion modes these modes are selected by programming the mode selection field adm to 10 b (single conversion) or to 11 b (continuous conversion). auto scan modes automatically convert a sequence of analog channels, beginning with the channel specified in bitfield adch and ending with channel 0, without requiring software to change the channel number. after starting the converter through bit adst, the busy flag adbsy will be set and the channel specified in bitfield adch will be converted. after the conversion is complete, the interrupt request flag adcir will be set and the converter will automatically start a new conversion of the next lower channel. adcir will be set after each completed conversion. after conversion of channel 0 the current sequence is complete. in single conversion mode the converter will automatically stop and reset bits adbsy and adst. in continuous conversion mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in adch. when bit adst is reset by software, while a conversion is in progress, the converter will complete the current sequence (including conversion of channel 0) and then stop and reset bit adbsy. figure 16-3 auto scan conversion mode example note: auto scan sequences that begin with channel numbers above 7 will generate (up to) 4 invalid results from channels 11 ? 8 which are not connected to input pins. starting an auto scan sequence with adch = e h will generate the following 15 results: 14, 13, 12, x, x, x, x, 7, 6, 5, 4, 3, 2, 1, 0. starting a sequence with adch = b h ? 8 h generates 4 ? 1 invalid results at the beginning of the sequence and therefore makes no sense in an application. # 2 result of channel: # x # 3 write adc_dat adc_dat full conversion of channel.. read of adc_dat; generate interrupt request # x # 3 # 3 # 2 interrupt request overrun error # 2 # 1 result lost mc_adc0001_autoscan # 3 # 1 # 1 # 0 adc_dat full; channnel 0 # 0 # 3 # 3 # 2
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-13 v2.2, 2004-01 adc_x1, v2.1 16.2.3 wait for read mode if in default mode of the adc a previous conversion result has not been read out of the result register by the time a new conversion is complete, the previous result is lost because it is overwritten by the new value, and the a/d overrun error interrupt request flag adeir will be set. in order to avoid error interrupts and the loss of conversion results especially when using continuous conversion modes, the adc can be switched to ? wait for read mode ? by setting bit adwr. if the result value has not been read by the time the current conversion is complete, the new result is stored in a temporary buffer and the next conversion is suspended (adst and adbsy will remain set in the meantime, but no end-of-conversion interrupt will be generated). after reading the previous value the temporary buffer is copied into adc_dat (generating an adcir interrupt) and the suspended conversion is started. this mechanism applies to both single and continuous conversion modes. note: while in standard mode continuous conversions are executed at a fixed rate (determined by the conversion time), in ? wait for read mode ? there may be delays due to suspended conversions. however, this only affects the conversions, if the cpu (or pec) cannot keep track with the conversion rate. figure 16-4 wait for read mode example result of channel: read of adc_dat; # x # 2 # 3 # 1 mc_adc0002_waitread # 0 request generate interrupt temp-latch full adc_dat full write adc_dat # x of channel.. conversion # 3 # 2 # 3 temp-latch hold result in 1 # 2 # 1 wait # 1 # 0 # 3 # 3 # 0
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-14 v2.2, 2004-01 adc_x1, v2.1 16.2.4 channel injection mode channel injection mode allows the conversion of a specific analog channel (also while the adc is running in a continuous or auto scan mode) without changing the current operating mode. after the conversion of this specific channel the adc continues with the original operating mode. channel injection mode is enabled by setting bit adcin and requires the wait for read mode (adwr = 1). the channel to be converted in this mode is specified in bitfield chnr of register adc_dat2. note: bitfield chnr in adc_dat2 is not modified by the a/d converter, but only the adres bitfield. since the channel number for an injected conversion is not buffered, bitfield chnr of adc_dat2 must never be modified during the sample phase of an injected conversion, otherwise the input multiplexer will switch to the new channel. it is recommended to only change the channel number with no injected conversion running. figure 16-5 channel injection example # x-2 write adc_dat2 int. request conversion of channel # y adc_dat2 full read adc_dat2 request conversion write adc_dat; injected read adc_dat adc_dat full of channel.. channel injection # x-1 # x+1 # x+1 # x # x # x # x-1 # x-1 # x-2 mc_adc0003_inject adeint # ... # x-4 # y # x-2 # x-3 # x-3 # x-3 # x-4 # x-4
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-15 v2.2, 2004-01 adc_x1, v2.1 a channel injection can be triggered in two ways: setting of the channel injection request bit adcrq via software a compare or a capture event of capture/compare register cc31 of the capcom2 unit, which also sets bit adcrq. the second method triggers a channel injection at a specific time, on the occurrence of a predefined count value of the capcom timers or on a capture event of register cc31. this can be either the positive, the negative, or both the positive and the negative edge of an external signal. in addition, this option allows recording the time of occurrence of this signal. note: the channel injection request bit adcrq will be set on any interrupt request of capcom2 channel cc31, regardless whether the channel injection mode is enabled or not. it is recommended to always clear bit adcrq before enabling the channel injection mode. after the completion of the current conversion (if any is in progress) the converter will start (inject) the conversion of the specified channel. when the conversion of this channel is complete, the result will be placed into the alternate result register adc_dat2, and a channel injection complete interrupt request will be generated, which uses the interrupt request flag adeir (for this reason the wait for read mode is required). note: the result of an injected conversion is directly written to adc_dat2. if the previous result has not been read in the meantime, it is overwritten. standard conversions are suspended if the temporary buffer is full.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-16 v2.2, 2004-01 adc_x1, v2.1 arbitration of conversions conversion requests that are activated while the adc is idle immediately trigger the respective conversion. if a conversion is requested while another conversion is currently in progress the operation of the a/d converter depends on the kind of the involved conversions (standard or injected). note: a conversion request is activated if the respective control bit (adst or adcrq) is toggled from 0 to 1, i.e. the bit must have been zero before being set. table 16-2 summarizes the adc operation in the possible situations. table 16-2 conversion arbitration conversion in progress new requested conversion standard injected standard abort running conversion, and start requested new conversion. 1) 1) if an injected conversion is pending when a standard conversion is re-started, the injected conversion is executed before the newly started standard conversion. complete running conversion, start requested conversion after that. injected complete running conversion, start requested conversion after that. complete running conversion, start requested conversion after that. bit adcrq will be 0 for the second conversion, however.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-17 v2.2, 2004-01 adc_x1, v2.1 16.3 automatic calibration the adc of the XC161 features automatic self-calibration. this calibration corrects gain errors, which are mainly due to process variation, and offset errors, which are mainly due to temperature changes. two types of calibration are supported: reset calibration performs a thorough basic calibration of the adc after a reset. in particular this is required after a power-on reset. post-calibration performs one small calibration step after each conversion. reset calibration after a reset, a thorough power-up calibration is performed automatically to correct gain and offset errors of the a/d converter. to achieve best calibration results, the reference voltages as well as the supply voltages must be stable during the power-up calibration. during the calibration sequence a series of calibration cycles is executed, where the step width for adjustments is reduced gradually. the total number of executed calibration cycles depends on the actual properties of the respective adc module. the maximum duration of the power-up calibration is 11,696 cycles of the basic clock f bc . status flag cal is set as long as this power-up calibration takes place. post-calibration after each conversion a small calibration step can be executed. for 8-bit and 10-bit conversions post-calibration is not mandatory in order not to exceed the total unadjusted error (tue) specified in the data sheet. post-calibration can be disabled by setting bit caloff in register adc_ctr0. when disabled, the post-calibration cycles are skipped which reduces the total conversion time. note: calibration may be disabled only after the reset calibration is complete.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-18 v2.2, 2004-01 adc_x1, v2.1 16.4 conversion timing control when a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. the time to load the capacitances is referred to as sample time. next the sampled voltage is converted to a digital value in successive steps, which correspond to the resolution of the adc. during these phases (except for the sample time) the internal capacitances are repeatedly charged and discharged via pins v aref and v agnd . the current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. the maximum current, however, that a source can deliver, depends on its internal resistance. the time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the XC161 relative to the cpu clock. the absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. this allows adjusting the a/d converter of the XC161 to the properties of the system: fast conversion can be achieved by programming the respective times to their absolute possible minimum. this is preferable for scanning high frequency signals. the internal resistance of analog source and analog supply must be sufficiently low, however. high internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum. this is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. the conversion rate in this case may be considerably lower, however. control bitfields for the timing control of the conversion and the sample phase two mechanisms are provided: standard timing control uses two 2-bit fields in register adc_con to select prescaler values for the general conversion timing and the duration of the sample phase. this provides compact control, while limiting the prescaler factors to a few steps. improved timing control uses two 6-bit fields in register adc_con1 (compatibility mode) or register adc_ctr2/adc_ctr2in (enhanced mode). this provides a wide range of prescaler factors, so the adc can be better adjusted to the internal and external system circumstances. improved timing control is selected by setting bit icst in register adc_con1 in compatibility mode, or by selecting enhanced mode.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-19 v2.2, 2004-01 adc_x1, v2.1 standard timing control standard timing control is performed by using two 2-bit fields in register adc_con. bitfield adctc (conversion time control) selects the basic conversion clock ( f bc ), used for the operation of the a/d converter. the sample time is derived from this conversion clock and controlled by bitfield adstc. the sample time is always a multiple of 8 f bc periods. table 16-3 lists the possible combinations. improved timing control to provide a finer resolution for programming of the timing parameters, wider bitfields have been implemented for timing control (the 2-bit bitfields in register adc_con are disregarded in all cases). in compatibility mode (with bit icst = 1), the bitfields in register adc_con1 are used for all conversions. in enhanced mode (bit md = 1), the bitfields in register adc_ctr2 are used for standard conversions. injected conversions use the bitfields in register adc_ctr2in. bitfield adctc (conversion time control) selects the basic conversion clock ( f bc ), used for the operation of the a/d converter. the sample time is derived from this conversion clock and controlled by bitfield adstc. the sample time is always a multiple of 4 f bc periods. table 16-4 lists the possible combinations. table 16-3 standard conversion and sample timing control adc_con.15|14 (adctc) a/d converter basic clock f bc 1) adc_con.13|12 (adstc) sample time t s 00 f adc /4 00 t bc 8 01 f adc /2 01 t bc 16 10 f adc /16 10 t bc 32 11 f adc /8 11 t bc 64 table 16-4 improved conversion and sample timing control adctc a/d converter basic clock f bc 1) 1) the limit values for f bc (see data sheet) must not be exceeded when selecting adctc and f adc . adstc sample time t s 00 ? 0000 b = 00 h f adc /1 00 ? 0000 b = 00 h t bc 8 00 ? 0001 b = 01 h f adc /2 00 ? 0001 b = 01 h t bc 12 00 ? 0010 b = 02 h f adc /3 00 ? 0010 b = 02 h t bc 16 ? f adc /(adctc + 1) ? t bc 4 (adstc + 2) 11 ? 1111 b = 3f h f adc /64 11 ? 1111 b = 3f h t bc 260
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-20 v2.2, 2004-01 adc_x1, v2.1 total conversion time examples the time for a complete conversion includes the sample time t s , the conversion itself (successive approximation and calibration), and the time required to transfer the digital value to the result register as shown in the example below (standard conversion timing). the timings refer to module clock cycles, where t adc = 1/ f adc . assumptions: f adc = 40 mhz (i.e. t adc = 25 ns), adctc = 01 b , adstc = 00 b basic clock: f bc = f adc /2 = 20 mhz, i.e. t bc = 50 ns sample time: t s = t bc 8 = 400 ns conversion 10-bit: with post-calibr.: t c10p = t s + 52 t bc + 6 t adc = (2600 + 400 + 150) ns = 3.15 s post-calibr. off: t c10 = t s + 40 t bc + 6 t adc = (2000 + 400 + 150) ns = 2.55 s conversion 8-bit: with post-calibr.: t c8p = t s + 44 t bc + 6 t adc = (2200 + 400 + 150) ns = 2.75 s post-calibr. off: t c8 = t s + 32 t bc + 6 t adc = (1600 + 400 + 150) ns = 2.15 s note: for the exact specification please refer to the data sheet of the selected derivative.
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-21 v2.2, 2004-01 adc_x1, v2.1 16.5 a/d converter interrupt control at the end of each conversion, interrupt request flag adcir in interrupt control register adc_cic is set. this end-of-conversion interrupt request may cause an interrupt to vector adcint, or it may trigger a pec data transfer which reads the conversion result from register adc_dat, e.g. to store it into a table in internal ram for later evaluation. the interrupt request flag adeir in register adc_eic will be set either, if a conversion result overwrites a previous value in register adc_dat (error interrupt in standard mode), or if the result of an injected conversion has been stored into adc_dat2 (end- of-injected-conversion interrupt). this interrupt request may be used to cause an interrupt to vector adeint, or it may trigger a pec data transfer. note: please refer to the general interrupt control register description for an explanation of the control fields. adc_cic adc conversion intr. ctrl. reg. sfr (ff98 h /cc h ) reset value: - - 00 h 1514131211109876543210 -gpx adc ir adc ie ilvl glvl - - - - - - - rw rwh rw rw rw adc_eic adc error intr. ctrl. reg. sfr (ff9a h /cd h ) reset value: - - 00 h 1514131211109876543210 -gpx ade ir ade ie ilvl glvl - - - - - - - rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) the analog/digital converter user ? s manual 16-22 v2.2, 2004-01 adc_x1, v2.1 16.6 interfaces of the adc module the adc is connected to its environment in different ways. internal connections the capture/compare signal cc31io of the capcom2 unit is connected to the adc, providing an optional trigger source for injected conversions. the 2 interrupt request lines of the adc are connected to the interrupt control block. external connections the analog input signals for the adc are connected with port 5 of the XC161 (input only). two dedicated pins ( v aref and v agnd ) provide the analog reference voltage for the conversion mechanism. figure 16-6 adc module io interface adc module v aref adc_eirq adc_cirq system control unit (scu) interrupt control block f adc adcdis cc31_cit capcom unit v gnd port p5 control mca05417 p5.0/an0 p5.1/an1 p5.2/an2 p5.3/an3 p5.4/an4 p5.5/an5 p5.6/an6 p5.7/an7 p5.8 p5.9 p5.10 p5.11 p5.12/an12 p5.13/an13 p5.14/an14 p5.15/an15 gpt external inputs
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-1 v2.2, 2004-01 cc12_x1, v2.1 17 capture/compare units the XC161 provides two, almost identical, capture/compare (capcom) units, which only differ in the way they are connected to the pins. each capcom unit provides 16 capture/compare channels, which interact with 2 timers. a capcom channel can capture the contents of a timer on specific internal or external events, or it can compare a timer ? s contents with given values, and modify output signals in case of a match. figure 17-1 sfrs associated with the capcom units mc_capcom120100_regist ers. vsd data registers control registers port registers t0, t0rel t01con t0ic t1ic t78con cc28ic-cc31ic p6, dp6 odp6 p7, dp7 e p9, dp9 odp9 odp7 e interrupt control syscon3 cc0...15 capcom1 register 0...15 cc0...15ic capcom1 intr. ctrl. reg. 0...15 ccm0...3 capcom1 mode ctrl. reg. 0...3 t01con capcom1 timer control reg. t0, t1 capcom1 ti mer regi ster t0/1rel capcom1 ti mer rel oad regi ster t0ic, t1ic capcom1 timer x intr. ctrl. reg. cc1/2_see capcom single event en. reg. cc1/2_sem capcom single event mode reg. cc1/2_drm capcom double reg. mode reg. cc1/2_out capcom output register cc1/2_ioc capcom input/outp. control reg. cc16...31 capcom2 register 16...31 cc16...31ic capcom2 intr. ctrl. reg. 16...31 ccm4...7 capcom2 mode ctrl. reg. 4...7 t78con capcom2 ti mer control reg. t7, t8 capcom2 ti mer regi s ter t7/8rel capcom2 ti mer rel oad regi s ter t7ic, t8ic capcom2 timer x intr. ctrl. reg. px port x data regi ster dpx port x di rec ti on control regi s ter odpx port x open drain control register altsel0px port x alternate outp. select reg.0 altsel1px port x alternate outp. select reg.1 syscon3 system ctrl. reg. 3 (per. mgmt.) t1, t1rel t7, t7rel t8, t8rel e e cc0-cc3 cc4-cc7 cc8-cc11 cc12-cc15 cc16-cc19 cc20-cc23 cc24-cc27 cc28-cc31 cc2_m7 cc2_m6 cc2_m5 cc2_m4 cc1_m3 cc1_m2 cc1_m1 cc1_m0 cc24ic-cc27ic cc20ic-cc23ic cc16ic-cc19ic cc12ic-cc15ic cc8ic-cc11ic cc4ic-cc7ic cc0ic-cc3ic e e e e t7ic t8ic p2, dp2 odp2 e p1l, p1h dp1l, dp1h e altsel0p6 e altsel0/1p7 e altsel0/1p9 altsel0p2 e altsel0p1l/h e e cc1/2_out cc1/2_see cc1/2_sem cc1/2_drm cc1/2_ioc
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-2 v2.2, 2004-01 cc12_x1, v2.1 with this mechanism, each capcom unit supports generation and control of timing sequences on up to 16 channels with a minimum of software intervention. from the programmer ? s point of view, the term ? capcom unit ? refers to a set of registers which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and their direction control bits (see also figure 17-1 ). a capcom unit is typically used to handle high speed io tasks such as pulse and waveform generation, pulse width modulation, or recording of the time when a specific event occurs. it also supports the implementation of up to 16 software-controlled interrupt events. each capcom unit consists of two 16-bit timers (t0/t1, t7/t8), each with its own reload register (txrel), and a bank of sixteen dual-purpose 16-bit capture/compare registers (ccy). the input clock for the capcom timers is programmable to several prescaled values of the module input clock ( f cc ), or it can be derived from the overflow/underflow of timer t6. t0/t7 may also operate in counter mode (from an external input), clocked by external events. each capture/compare register may be programmed individually for capture or compare operation, and each register may be allocated to either of the two timers. each capture/compare register has one signal associated with it, which serves as an input signal for the capture operation or as an output signal for the compare operation. the capture operation causes the current timer contents to be latched into the respective capture/compare register, triggered by an event (transition) on the associated input signal. this event also activates the associated interrupt request line. the compare operation may cause an output signal transition on the associated output signal, when the allocated timer increments to the value stored in a capture/compare register. the compare match event also activates the associated interrupt request line. in double-register compare mode a pair of registers controls one common output signal. the compare output signals are available via a dedicated output register, and may also control the output latches of the connected port pins. the output path can be selected. for the switching of the output signals two timing schemes (see section 17.8 ) can be selected: in staggered mode 1) the output signals are switched consecutively in 8 steps, which distributes the switching steps over a certain time. in staggered mode, the maximum resolution is 8 t cc . in non-staggered mode the output signals are switched immediately at the same time. in non-staggered mode, the maximum resolution is 1 t cc . figure 17-2 shows the basic structure of a capcom unit. 1) staggered mode is compatible with the capcom units of previous 16-bit controllers.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-3 v2.2, 2004-01 cc12_x1, v2.1 figure 17-2 capcom unit block diagram timer t0/t7 sixteen 16-bit capture/ compare registers timer t1/t8 reload reg. t1rel/t8rel t0/t7 input control mode control (capture or compare) t1/t8 input control mcb05418 reload reg. t0rel/t7rel t0irq, t7irq ccxirq ccxirq t1irq, t8irq ccxirq f cc t0in/t7in t6ouf ccxio ccxio ccxio f cc t6ouf capcom1 provides channels x = 0 ? 15, capcom2 provides channels x = 16 ? 31. (see signals ccxio and ccxirq)
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-4 v2.2, 2004-01 cc12_x1, v2.1 17.1 the capcom timers the primary use of the timers t0/t7 and t1/t8 is to provide two independent time bases for the capture/compare channels of each unit. the maximum resolution is 8 t cc in staggered mode, and 1 t cc in non-staggered mode. the basic structure of the two timers, illustrated in figure 17-3 , is identical, except for the input pin (see mark). figure 17-3 block diagram of a capcom timer note: when an external input signal is connected to the input lines of both t0 and t7, these timers count the input signal synchronously. thus, the two timers can be regarded as one timer whose contents can be compared with 32 compare registers. the functions of the capcom timers are controlled via the bit-addressable control registers t01con and t78con. the high-byte of t01con controls t1, the low-byte of t01con controls t0. the high-byte of t78con controls t8, the low-byte of t78con controls t7. the control options are identical for all four timers (except for external input). in all modes, the timers are always counting upward. the current timer values are accessible for the cpu in the timer registers tx, which are non bit-addressable registers. when the cpu writes to a register tx in the state immediately before the respective timer increment or reload is to be performed, the cpu write operation has priority and the increment or reload is disabled to guarantee correct timer operation. mcb05419 txirq count txr reload reg. txrel timer tx to capure/compare register array txi txm x = 0, 1, 7, 8 t6ouf mux txi txin prescaler txi f tx f cc edge select
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-5 v2.2, 2004-01 cc12_x1, v2.1 the timer run flags txr allow the starting and stopping of the timers. the following description of the timer modes and operation always applies to the enabled state of the timers, i.e. the respective run flag is assumed to be set. cc1_t01con timer 0/1 control register sfr (ff50 h /a8 h ) reset value: 0000 h 1514131211109876543210 - t1r - t1m t1i - t0r - t0m t0i - rw - rw rw - rw - rw rw cc2_t78con timer 7/8 control register sfr (ff20 h /90 h ) reset value: 0000 h 1514131211109876543210 - t8r - t8m t8i - t7r - t7m t7i - rw - rw rw - rw - rw rw field bits type description txr 14, 6 rw timer/counter tx run control 0 timer/counter tx is disabled 1 timer/counter tx is enabled txm 11, 3 rw timer/counter tx mode selection 0 timer mode 1 counter mode txi [10:8], [2:0] rw timer/counter tx input selection timer mode (txm = 0): input frequency f tx = f cc /2 (+3) or f cc /2 () , depending on (non-)staggered mode, see table 17-1 counter mode (txm = 1): 000 overflow/underflow of gpt timer t6 001 positive (rising) edge on pin txin 010 negative (falling) edge on pin txin 011 any edge (rising and falling) on pin txin 1xx reserved. do not use this combination! note: for timers t1 and t8 the only option in counter mode is 000 b . t1 and t8 stop in other cases.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-6 v2.2, 2004-01 cc12_x1, v2.1 timer mode in timer mode (txm = 0), the input clock for a capcom timer is derived from f cc , divided by a programmable prescaler. each timer has its own individual prescaler, controlled through the individual bitfields txi in the timer control registers t01con and t78con. the input frequency f tx for a timer tx and its resolution r tx are determined by the following formulas: staggered mode: (17.1) non-staggered mode: (17.2) when a timer overflows from ffff h to 0000 h , it is reloaded with the value stored in its respective reload register txrel. the reload value determines the period p tx between two consecutive overflows of tx as follows: staggered mode: (17.3) non-staggered mode: (17.4) after a timer has been started by setting its run flag (txr), the first increment will occur within the time interval which is defined by the selected timer resolution. all further increments occur exactly after the time defined by the timer resolution. examples for timer input frequencies, resolution and periods, which result from the selected prescaler option in txi when using a 40 mhz clock, are listed in table 17-1 below. the numbers for the timer periods are based on a reload value of 0000 h . note that some numbers may be rounded. f tx mhz [] f cc mhz [] 2 3 + () ------------------------- - = r tx s [] 2 3 + () f cc mhz [] ------------------------- - = f tx mhz [] f cc mhz [] 2 ------------------------- - = r tx s [] 2 f cc mhz [] ------------------------- - = p tx s [] 2 16 ? () 2 3 + () f cc mhz [] ------------------------------------------------------------------------- = p tx s [] 2 16 ? () 2 f cc mhz [] --------------------------------------------------------------- - =
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-7 v2.2, 2004-01 cc12_x1, v2.1 table 17-1 timer tx input clock selection for timer mode, f cc = 40 mhz txi prescaler input frequency resolution period non-staggered mode 000 b 8 5 mhz 200 ns 13.11 ms 001 b 16 2.5 mhz 400 ns 26.21 ms 010 b 32 1.25 mhz 800 ns 52.43 ms 011 b 64 625 khz 1.6 s 104.86 ms 100 b 128 312.5 khz 3.2 s 209.72 ms 101 b 256 156.25 khz 6.4 s 419.43 ms 110 b 512 78.125 khz 12.8 s 838.86 ms 111 b 1024 39.0625 khz 25.6 s 1677.72 ms non-staggered mode 000 b 1 40 mhz 25 ns 1.6384 ms 001 b 2 20 mhz 50 ns 3.2768 ms 010 b 4 10 mhz 100 ns 6.5536 ms 011 b 8 5 mhz 200 ns 13.11 ms 100 b 16 2.5 mhz 400 ns 26.21 ms 101 b 32 1.25 mhz 800 ns 52.43 ms 110 b 64 625 khz 1.6 s 104.86 ms 111 b 128 312.5 khz 3.2 s 209.72 ms
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-8 v2.2, 2004-01 cc12_x1, v2.1 counter mode in counter mode (txm = 1), the input clock of a capcom timer is either derived from an associated external input pin, t0in/t7in, or from the over-/underflows of gpt timer t6. using an external signal connected to pin txin as a counting signal is only possible for timers t0 and t7. the only counter option for timers t1 and t8 is using the over- /underflows of the gpt timer t6 (selected by txi = 000 b ). bitfields t0i/t7i are used to select either a positive, a negative, or both a positive and a negative transition of the external signal at pin t0in/t7in to trigger an increment of timer t0/t7. please note that certain criteria must be met for the external signal and the port pin programming for this mode in order to operate properly. these conditions are detailed in chapter 17.10 . timer overflow and reload when a capcom timer contains the value ffff h at the time a new count trigger occurs, a timer interrupt request is generated, and the timer is loaded with the contents of its associated reload register txrel. the timer then resumes incrementing with the next count trigger starting from the reloaded value. the reload registers txrel are not bitaddressable. after reset, they contain the value 0000 h .
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-9 v2.2, 2004-01 cc12_x1, v2.1 17.2 capcom timer interrupts upon a timer overflow the corresponding timer interrupt request flag txir for the respective timer will be set. this flag can be used to generate an interrupt or trigger a pec service request, when enabled by the respective interrupt enable bit txie. each timer has its own bitaddressable interrupt control register and its own interrupt vector. the organization of the interrupt control registers txic is identical with the other interrupt control registers. note: please refer to the general interrupt control register description for an explanation of the control fields. cc1_t0ic capcom t0 intr. ctrl. reg. sfr (ff9c h /ce h ) reset value: - - 00 h 1514131211109876543210 - gpx t0ir t0ie ilvl glvl - - - - - - - rw rwh rw rw rw cc1_t1ic capcom t1 intr. ctrl. reg. sfr (ff9e h /cf h ) reset value: - - 00 h 1514131211109876543210 - gpx t1ir t1ie ilvl glvl - - - - - - - rw rwh rw rw rw cc2_t7ic capcom t7 intr. ctrl. reg. esfr (f17a h /be h ) reset value: - - 00 h 1514131211109876543210 - gpx t7ir t7ie ilvl glvl - - - - - - - rw rwh rw rw rw cc2_t8ic capcom t8 intr. ctrl. reg. esfr (f17c h /bf h ) reset value: - - 00 h 1514131211109876543210 - gpx t8ir t8ie ilvl glvl - - - - - - - rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-10 v2.2, 2004-01 cc12_x1, v2.1 17.3 capture/compare channels the 16-bit capture/compare registers cc0 through cc15 (cc16 through cc31) are used as data registers for capture or compare operations with respect to timers t0/t7 and t1/t8. the capture/compare registers are not bit-addressable. the functions of the 16 capture/compare registers of a unit are controlled by 4 bit- addressable 16-bit mode control registers, named cc1_m0 ? cc1_m3 (cc2_m4 ? cc2_m7), which are all organized identically (see description below). each register contains the bits for mode selection and timer allocation for four capture/comp. registers. capture/compare registers for the capcom1 unit (cc15 ? cc0) cc1_m0 capcom mode ctrl. reg. 0 sfr (ff52 h /a9 h ) reset value: 0000 h 1514131211109876543210 acc 3 mod3 acc 2 mod2 acc 1 mod1 acc 0 mod0 rw rw rw rw rw rw rw rw cc1_m1 capcom mode ctrl. reg. 1 sfr (ff54 h /aa h ) reset value: 0000 h 1514131211109876543210 acc 7 mod7 acc 6 mod6 acc 5 mod5 acc 4 mod4 rw rw rw rw rw rw rw rw cc1_m2 capcom mode ctrl. reg. 2 sfr (ff56 h /ab h ) reset value: 0000 h 1514131211109876543210 acc 11 mod11 acc 10 mod10 acc 9 mod9 acc 8 mod8 rw rw rw rw rw rw rw rw cc1_m3 capcom mode ctrl. reg. 3 sfr (ff58 h /ac h ) reset value: 0000 h 1514131211109876543210 acc 15 mod15 acc 14 mod14 acc 13 mod13 acc 12 mod12 rw rw rw rw rw rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-11 v2.2, 2004-01 cc12_x1, v2.1 capture/compare registers for the capcom2 unit (cc31 ? cc16) cc2_m4 capcom mode ctrl. reg. 4 sfr (ff22 h /91 h ) reset value: 0000 h 1514131211109876543210 acc 19 mod19 acc 18 mod18 acc 17 mod17 acc 16 mod16 rw rw rw rw rw rw rw rw cc2_m5 capcom mode ctrl. reg. 5 sfr (ff24 h /92 h ) reset value: 0000 h 1514131211109876543210 acc 23 mod23 acc 22 mod22 acc 21 mod21 acc 20 mod20 rw rw rw rw rw rw rw rw cc2_m6 capcom mode ctrl. reg. 6 sfr (ff26 h /93 h ) reset value: 0000 h 1514131211109876543210 acc 27 mod27 acc 26 mod26 acc 25 mod25 acc 24 mod24 rw rw rw rw rw rw rw rw cc2_m7 capcom mode ctrl. reg. 7 sfr (ff28 h /94 h ) reset value: 0000 h 1514131211109876543210 acc 31 mod31 acc 30 mod30 acc 29 mod29 acc 28 mod28 rw rw rw rw rw rw rw rw field bits type description accy 15, 11, 7, 3 rw allocation bit for capcom register ccy 0 ccy allocated to timer t0 or t7, respectively 1 ccy allocated to timer t1 or t8, respectively mody [14:12], [10:8], [6:4], [2:0] rw mode selection for capcom register ccy see table 17-2 .
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-12 v2.2, 2004-01 cc12_x1, v2.1 each of the registers ccy may be individually programmed for capture mode or for one of 4 different compare modes, and may be allocated individually to one of the two timers of the respective capcom unit. a special double-register compare mode combines two registers to act on one common output signal. when capture or compare operations are disabled for one of the ccy registers, it may be used for general purpose variable storage. the detailed discussion of the capture and compare modes is valid for all the capture/compare channels, so registers, bits and pins are only referenced by a placeholder. note: a capture or compare event on channel 31 may be used to trigger a channel injection on the XC161 ? s a/d converter if enabled. table 17-2 selection of capture modes and compare modes mode mody selected operating mode disabled 0 0 0 disable capture and compare modes the respective capcom register may be used for general variable storage. capture 0 0 1 capture on positive transition (rising edge) at pin ccyio 0 1 0 capture on negative transition (falling edge) at pin ccyio 0 1 1 capture on positive and negative transition (both edges) at pin ccyio compare 1 0 0 compare mode 0: interrupt only several interrupts per timer period. can enable double-register compare mode for bank2 registers. 1 0 1 compare mode 1: toggle output pin on each match several compare events per timer period. can enable double-register compare mode for bank1 registers. 1 1 0 compare mode 2: interrupt only only one interrupt per timer period. 1 1 1 compare mode 3: set output pin on each match reset output pin on each timer overflow; only one interrupt per timer period.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-13 v2.2, 2004-01 cc12_x1, v2.1 17.4 capture mode operation in capture mode, the current contents of a capcom timer are latched (captured) into the respective capture/compare register in response to an external event. this is used, for example, to record the time at which an external event has occurred, or to measure the distance between two external events in timer increments. the event to cause a capture of a timer ? s contents can be programmed to be either the positive, the negative, or both the positive and the negative transition of the external signal connected to the input pin. this triggering transition is selected by bitfield mody in the respective mode control register. when the selected external signal transition occurs, the selected timer ? s contents is latched into the capture/compare register and the respective interrupt request line ccyirq is activated. this can cause an interrupt or pec service request, when enabled. note: a capture input can be used as an additional external interrupt input. the capture operation can be disregarded in this case. either the contents of timer t0/t7 or t1/t8 can be captured, selected by the timer allocation control bit accy in the respective mode control register. figure 17-4 capture mode block diagram for capture operation, the respective pin must be programmed for input. to ensure that a transition of the input signal is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. this information can be found in section 17.10 . mcb05420 mux timer t0/t7 accy timer t1/t8 capture register ccy interrupt requests mody ccyio ccyirq input clock edge select
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-14 v2.2, 2004-01 cc12_x1, v2.1 17.5 compare mode operation the compare modes allow triggering of events (interrupts and/or output signal transitions) or generation of pulse trains with minimum software overhead. in all compare modes, the 16-bit value stored in a capture/compare register ccy (in the following also referred to as ? compare value ? ) is continuously compared with the contents of the allocated timer (t0/t7 or t1/t8). if the current timer contents match the compare value, the interrupt request line associated with register ccy is activated and, depending on the compare mode, an output signal can be generated at the corresponding output pin ccyio. four different compare modes are available, which can be selected individually for each of the capture/compare registers by bitfield mody in the respective mode control register. modes 0 and 2 do not influence the output signals. in the following, each mode is described in detail. in addition to these ? single-register ? modes, a ? double-register ? compare mode enables two registers to operate on the same pin. this feature can further reduce software overhead, as two different compare values can be programmed to control a sequence of transitions for a signal. see section 17.5.5 for details for this operation. in all compare modes, the comparator performs an ? equal to ? comparison. this means, a match is only detected when the timer contents are equal to the contents of a compare register. in addition, the comparator is only enabled in the clock cycle directly after the timer was incremented by hardware. this is done to prevent repeated matches if the timer does not operate with the highest possible input clock (either in timer or counter mode). in this case, the timer contents would remain at the same value for several or up to thousands of cycles. this operation has the side-effect, that software modifications of the timer contents will have no effect regarding the comparator. if a timer is set by software to the same value stored in one of the compare registers, no match will be detected. if a compare register is set to a value smaller than the current timer contents, no action will take place. for the exact operation of the port output function, please see section 17.6 . when two or more compare registers are programmed to the same compare value 1) , their corresponding interrupt request flags will be set and the selected output signals will be generated after the allocated timer is incremented to this compare value. further compare events on the same compare value are disabled 2) until the timer is incremented again or written to by software. after a reset, compare events for register ccy will only become enabled, if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register. 1) in staggered mode these interrupts and output signals are generated sequentially (see section 17.8 ). 2) even if more compare cycles are executed before the timer increments (lower timer frequency) a given compare value only results in one single compare event.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-15 v2.2, 2004-01 cc12_x1, v2.1 17.5.1 compare mode 0 this is an interrupt-only mode which can be used for software timing purposes. in this mode, the interrupt request line ccyirq is activated each time a match is detected between the contents of the compare register ccy and the allocated timer. a match means, the contents of the timer are equal to ( ? = ? ) the contents of the compare register. several of these compare events are possible within a single timer period, if the compare value in register ccy is updated during the timer period. the corresponding port signal ccyio is not affected by compare events in this mode and can be used as general purpose io. note: if compare mode 0 is programmed for one of the bank2 registers the double- register compare mode may be enabled for this register (see chapter 17.5.5 ). 17.5.2 compare mode 1 this is a compare mode which influences the associated output signal. besides this, the basic operation is as in compare mode 0. each time a match is detected between the contents of the compare register ccy and the allocated timer, the interrupt request line ccyirq is activated. in addition, the associated output signal is toggled. several of these compare events are possible within a single timer period, if the compare value in register ccy is updated during the timer period. note: if compare mode 1 is programmed for one of the bank1 registers the double- register compare mode may be enabled for this register (see section 17.5.5 ). for the exact operation of the port output signal, please see section 17.6 .
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-16 v2.2, 2004-01 cc12_x1, v2.1 figure 17-5 compare mode 0 and 1 block diagram note: the signal remains unaffected in compare mode 0. figure 17-6 illustrates a few example cases for compare modes 0 and 1. in all examples, the reload value of the used timer is set to fff9 h . when the timer overflows, it starts counting from this value upwards. in case 1 , register ccy contains the value fffc h . when the timer reaches this value, a match is detected, and the interrupt request line ccyirq is activated. in compare mode 0, this is all that will happen. in compare mode 1, additionally the associated port output is toggled, causing an inversion of the output signal. if the contents of register ccy are not changed, this operation will take place each time the timer reaches the programmed compare value. in case 2 , software reloads the compare register ccy with ffff h after the first match with fffc h has occurred. as the timer continues to count up, it finally reaches this new compare value, and a new match is detected, activating the interrupt request line (both modes) and toggling the output signal (compare mode 1). if then the compare value is left unchanged, the next match will occur when the timer reaches ffff h again. this example illustrates, that further compare matches are possible within the current timer period (this is in contrast to compare modes 2 and 3). mcb05421 mux timer t0/t7 accy mode & output ctrl. ccyirq to port logic timer t1/t8 mode control semy seey compare register ccy comparator = ? mody t0irq, t7irq t1irq, t8irq mode 1 only!
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-17 v2.2, 2004-01 cc12_x1, v2.1 figure 17-6 examples for compare modes 0 and 1 in case 3 , a new compare value, higher than the current timer contents, causes a new match within the current timer period. the compare register is reloaded with fffa h after the first match (at fffc h ). however, the timer has already passed this value. thus, it will take until the timer reaches fffa h in the following timer period to cause the desired compare match. reloading register ccy now with a value higher than the current timer contents will cause the next match within this period. in case 4 , the compare values are equal to the timer reload value or to the maximum count value, ffff h . mct05422 ccxio case 1 ccxio case 2 cc0 = ffff ccxio case 3 ccxio case 4 fffc fffd fffe ffff fff9 fffa fffb fffc fffd fffe ffff fff9 fffa fffb timer contents cc0 = fffa cc0 = fffd cc0 = fffc cc0 = fff9 cc0 = fffa cc0 = fffc cc0 = ffff cc0 = fffb symbolizes activation of the interrupt request line ccyirq reload value = fff9
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-18 v2.2, 2004-01 cc12_x1, v2.1 17.5.3 compare mode 2 compare mode 2 is an interrupt-only mode similar to compare mode 0. the main difference is that only one compare match, corresponding to one interrupt request, is possible within a given timer period. when a match is detected in compare mode 2 for the first time within a count period of the allocated timer, the interrupt request line ccyirq is activated. in addition, all further compare matches within the current timer period are disabled, even if a new compare value, higher than the current timer contents, would be written to the register. this blocking is only released when the allocated timer overflows. a new compare value written to the compare register after the first match will only go into effect within the following timer period. 17.5.4 compare mode 3 compare mode 3 is based on compare mode 2, but additionally influences the associated port pin. only one compare event is possible within one timer period. when a match is detected in compare mode 3 for the first time within a count period of the allocated timer, the interrupt request line ccyirq is activated, and the associated output signal is set to 1. in addition, all further compare matches within the current timer period are disabled, even if a new compare value, higher than the current timer contents, would be written to the register. this blocking is only released when the allocated timer overflows. a new compare value written to the compare register after the first match will only go into effect within the following timer period. the overflow signal is also used to reset the associated output signal to 0. special attention has to be paid when the compare value is set equal to the timer reload value. in this case, the compare match signal would try to set the output signal, while the timer overflow tries to reset the output signal. this conflict is avoided such that the state of the output signal is left unchanged in this case. note: when the compare value is changed from a value above the current timer contents to a value below the current timer contents, the new value is not recognized before the next timer period. for the exact operation of the port output signal, please see section 17.6 .
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-19 v2.2, 2004-01 cc12_x1, v2.1 figure 17-7 compare mode 2 and 3 block diagram note: the port latch and signal remain unaffected in compare mode 2. figure 17-8 illustrates a few timing examples for compare modes 2 and 3. in all examples, the reload value of the used timer is set to fff9 h . when the timer overflows, it starts counting from this value upwards. in case 1 , register ccy contains the value fffc h . when the timer reaches this value, a match is detected, and the interrupt request line ccyirq is activated. in compare mode 2, this is all that will happen. in compare mode 3, additionally the associated port output is set to 1. the timer continues to count, and finally reaches its overflow. at this point, the port output is reset to 0 again. note that, although not shown in the diagrams, the overflow signal of the timer also activates the associated interrupt request line txirq. if the contents of register ccy are not changed, the port output will be set again during the following timer period, and reset again when the timer overflows. this operation is ideal for the generation of a pulse width modulated (pwm) signal with a minimum of software overhead. the pulse width is varied by changing the compare value accordingly. in case 2 , the compare operation is blocked after the first match within a timer period. after the first match at fffc h , the interrupt request is generated and the port output is set. in addition, further compare matches are disabled. if now a new compare value is written to register ccy, no interrupt request and no port output influence will take place, although the new compare value is higher than the current timer contents. only after the overflow of the timer, the compare logic is enabled again, and the next match will be mcb05423 mux mux timer t0/t7 accy accy mode & output ctrl. ccyirq to port logic timer t1/t8 mode control semy seey compare register ccy comparator = ? mody t0irq, t7irq t1irq, t8irq mode 3 only!
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-20 v2.2, 2004-01 cc12_x1, v2.1 detected at ffff h . one can see, that this operation is ideal for pwm generation, as software can write a new compare value regardless of whether this value is higher or lower than the current timer contents. it is assured that the new value (usually written to the compare register in the appropriate interrupt service routine) will only go into effect during the following timer period. figure 17-8 timing example for compare modes 2 and 3 note: in compare mode 2, only interrupt requests are generated, in mode 3, also the output signals are generated. in case 3 , further examples for the operation of the compare match blocking are illustrated. in case 4 , a new compare value is written to a compare register before the first match within the timer period. one can see that, of course, the originally programmed compare match (at fffa h ) will not take place. the first match will be detected at fffc h . however, it is important to note that the reprogramming of the compare register took place asynchronously - this means, the register was written to without any regard to the current contents of the timer. this is dangerous in the sense that the effect of such an asynchronous reprogramming is not easily predictable. if the timer would have already reached the originally programmed compare value of fffa h by the time the software mct05424 ccxio case 1 ccxio case 2 cc0 = ffff ccxio case 3 ccxio case 4 fffc fffd fffe ffff fff9 fffa fffb fffc fffd fffe ffff fff9 fffa fffb timer contents cc0 = fffa cc0 = fffc cc0 = fffa cc0 = fffc reload value = fff9
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-21 v2.2, 2004-01 cc12_x1, v2.1 wrote to the register, a match would have been detected and the reprogramming would go into effect during the next timer period. the examples in figure 17-9 show special cases for compare modes 2 and 3. case 1 illustrates the effect when the compare value is equal to the reload value of the timer. an interrupt is generated in both modes. in mode 3, the output signal is not affected - it remains at the high level. setting the compare value equal to the reload value easily enables a 100% duty cycle signal for pwm generation. the important advantage here is that the compare interrupt is still generated and can be used to reload the next compare value. thus, no special treatment is required for this case (see case 3). cases 2, 4, and 5 show different options for the generation of a 0% duty cycle signal. case 2 shows an asynchronous reprogramming of the compare value equal to the reload value. at the end of the current timer period, a compare interrupt will be generated, which enables software to set the next compare value. the disadvantage of this method is that at least two timer periods will pass until a new regular compare value can go into effect. the compare match with the reload value fff9 h will block further compare matches during that timer period. this is additionally illustrated by case 4. figure 17-9 special cases in compare modes 2 and 3 mct05425 cc0 = fff9 int. int. ccxio case 1 int. ccxio case 2 int. cc0 = fff9 int. ccxio case 3 int. cc0 = fffb ccxio case 4 int. cc0 = fff9 int. cc0 = fffc no comp. ccxio case 5 int. cc0 = fffc int. cc0 = fff8 fffc fffd fffe ffff fff9 fffa fffb fffc fffd fffe ffff fff9 fffa fffb timer contents reload value = fff9 cc0 = fff9 int.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-22 v2.2, 2004-01 cc12_x1, v2.1 case 5 shows an option to get around this problem. here, the compare register is reloaded with fff8 h , a value which is lower than the timer reload value. thus, the timer will never reach this value, and no compare match will be detected. the output signal will be set to 0 after the first timer overflow. however, after the second overflow, software now reloads the compare register with a regular compare value. as no compare blocking has taken place (since there was no compare match), the newly written compare value will go into effect during the current timer period. 17.5.5 double-register compare mode the double-register compare mode makes it possible to further reduce software overhead for a number of applications. in this mode, two compare registers work together to control one output. this mode is selected via the drm register, or by a special combination of compare modes for the two registers. for double-register compare mode, the 16 capture/compare registers of a capcom unit are regarded as two banks of 8 registers each. the lower eight registers form bank1, while the upper eight registers form bank2. for double-register mode, a bank1 register and a bank2 register form a register pair. both registers of this register pair operate on the pin associated with the bank1 register. the relationship between the bank1 and bank2 register of a pair and the effected output pins for double-register compare mode is listed in table 17-3 . the double-register compare mode can be programmed individually for each register pair. double-register compare mode can be selected via a certain combination of compare modes for the two registers of a pair. the bank1 register must be programmed table 17-3 register pairs for double-register compare mode capcom1 unit capcom2 unit register pair used output pin control bitfield in cc1drm register pair used output pin control bitfield in cc2drm bank 1 bank 2 bank 1 bank 2 cc0 cc8 cc0io dr0m cc16 cc24 cc16io dr0m cc1 cc9 cc1io dr1m cc17 cc25 cc17io dr1m cc2 cc10 cc2io dr2m cc18 cc26 cc18io dr2m cc3 cc11 cc3io dr3m cc19 cc27 cc19io dr3m cc4 cc12 cc4io dr4m cc20 cc28 cc20io dr4m cc5 cc13 cc5io dr5m cc21 cc29 cc21io dr5m cc6 cc14 cc6io dr6m cc22 cc30 cc22io dr6m cc7 cc15 cc7io dr7m cc23 cc31 cc23io dr7m
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-23 v2.2, 2004-01 cc12_x1, v2.1 for mode 1 (with port influence), while the bank2 register must be programmed for mode 0 (interrupt-only). double-register compare mode can be controlled (this means, enabled or disabled) for each register pair via the associated control bitfield drxm in register cc1_drm or cc2_drm, respectively. double-register compare mode can be controlled individually for each of the register pairs. in the block diagram of the double-register compare mode ( figure 17-10 ), a bank2 register will be referred to as ccz, while the corresponding bank1 register will be referred to as ccy. cc1_drm double-reg. cmp. mode reg. sfr (ff5a h /ad h ) reset value: 0000 h 1514131211109876543210 dr7m dr6m dr5m dr4m dr3m dr2m dr1m dr0m rw rw rw rw rw rw rw rw cc2_drm double-reg. cmp. mode reg. sfr (ff2a h /95 h ) reset value: 0000 h 1514131211109876543210 dr7m dr6m dr5m dr4m dr3m dr2m dr1m dr0m rw rw rw rw rw rw rw rw field bits type description drxm [1:0], [3:2], [5:4], [7:6], [9:8], [11:10], [13:12], [15:14] rw double register x compare mode selection 00 drm is controlled via the combination of compare modes 1 and 0 (compatibility mode) 01 drm disabled regardless of compare modes 10 drm enabled regardless of compare modes 11 reserved note: ? x ? indicates the register pair index in a bank.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-24 v2.2, 2004-01 cc12_x1, v2.1 figure 17-10 double-register compare mode block diagram when a match is detected for one of the two registers in a register pair (ccy or ccz), the associated interrupt request line (ccyirq or cczirq) is activated, and pin ccyio, corresponding to the bank1 register ccy, is toggled. the generated interrupt always corresponds to the register that caused the match. note: if a match occurs simultaneously for both register ccy and register ccz of the register pair, pin ccyio will be toggled only once, but two separate compare interrupt requests will be generated. each of the two registers of a pair can be individually allocated to one of the two timers in the capcom unit. this offers a wide variety of applications, as the two timers can run in different modes with different resolution and frequency. however, this might require sophisticated software algorithms to handle the different timer periods. note: the signals cczio (which do not serve for double-register compare mode) may be used for general purpose io. mode control semy seey comp. = ? mux timer t0/t7 timer t1/t8 accy accz drym mody ccyirq mux mode & output ctrl. to port logic mcb05426 comparator = ? compare register ccz cczirq z = y + 8 mode control semz seez drym modz compare register ccy
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-25 v2.2, 2004-01 cc12_x1, v2.1 17.6 compare output signal generation this section discusses the interaction between the capcom unit and the port logic. the block diagram illustrated in figure 17-11 details the logic of the block ? mode & output control ? , shown in figure 17-5 , figure 17-7 , and figure 17-10 . each output signal is latched in its associated bit of the respective output latch register ccx_out. the individual bits are updated each time an associated compare event occurs. the bits of these registers are connected to the respective port pins as an alternate output function of a port line. compare signals can also directly affect the associated port output latch px. in this case, the port latch must be selected for the respective pin. the direct port latch option is disabled in non-staggered mode or it can be disabled by setting bit pl in register ccx_ioc. register ccx_out is always updated in parallel to the update of the port output latch. cc1_out compare output reg. sfr (ff5c h /ae h ) reset value: 0000 h 1514131211109876543210 cc 15 io cc 14 io cc 13 io cc 12 io cc 11 io cc 10 io cc9 io cc8 io cc7 io cc6 io cc5 io cc4 io cc3 io cc2 io cc1 io cc0 io rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh cc2_out compare output reg. sfr (ff2c h /96 h ) reset value: 0000 h 1514131211109876543210 cc 15 io cc 14 io cc 13 io cc 12 io cc 11 io cc 10 io cc9 io cc8 io cc7 io cc6 io cc5 io cc4 io cc3 io cc2 io cc1 io cc0 io rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description ccyio 15 ? 0rwh compare output for channel y alternative port output for the associated port pin.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-26 v2.2, 2004-01 cc12_x1, v2.1 figure 17-11 port output block diagram for compare modes note: a compare output signal is visible at the pin only in compare modes 1 or 3. the output signal of a compare event can either be a 1, a 0, the complement of the current level, or the previous level. the block ? output value control ? determines the correct new level based on the compare event, the timer overflow signal, and the current states of the port and out latches. for the output toggle function (e.g. in compare mode 1), the state of the output latch is read, inverted, and then written back. the associated output pins either drives the port latch signal or the out signal, selected by register altsel (see figure 17-11 ). note: if the port output latch is written to by software at the same time it would be altered by a compare event, the software write will have priority. in this case the hardware- triggered change will not become effective. mcb05427 txov mux altsel0pn 0 1 port latch & out latch >1 _ output value control mody compare match stag pl direction driver port pin pm.n capcom logic port logic
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-27 v2.2, 2004-01 cc12_x1, v2.1 17.7 single event operation if an application requires that one and only one compare event needs to take place (within a certain time frame), single event operation helps to reduce software overhead and to eliminate the need for fast reaction upon events. in order to achieve a single event operation without this feature, software would have to either disable the compare mode or write a new value, which is outside of the count range of the timer, into the compare register, after the programmed compare match has taken place. thus, usually an interrupt service routine is required to perform this operation. interrupt response time may be critical if the timer period is very short - the disable operation needs to be completed before the timer would reach the same value again. the single event operation eliminates the need for software to react after the first compare match. the complete operation can be set up before the event, and no action is required after the event. the hardware takes care of generating only one event, and then disabling all further compare matches. this option is programmed via the single event mode register ccx_sem and the single event enable register ccx_see. each register provides one bit for each ccy register of a unit. cc1_sem single event mode ctrl. reg. sfr (fe28 h /14 h ) reset value: 0000 h 1514131211109876543210 sem 15 sem 14 sem 13 sem 12 sem 11 sem 10 sem 9 sem 8 sem 7 sem 6 sem 5 sem 4 sem 3 sem 2 sem 1 sem 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw cc2_sem single event mode ctrl. reg. sfr (fe2c h /16 h ) reset value: 0000 h 1514131211109876543210 sem 15 sem 14 sem 13 sem 12 sem 11 sem 10 sem 9 sem 8 sem 7 sem 6 sem 5 sem 4 sem 3 sem 2 sem 1 sem 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description semy 15 ? 0rw single event mode control 0 single event mode disabled for channel y 1 single event mode enabled for channel y
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-28 v2.2, 2004-01 cc12_x1, v2.1 to setup a single event operation for a ccy register, software first programs the desired compare operation and compare value, and then sets the respective bit in register ccx_sem to enable the single event mode. at last, the respective event enable bit in register ccx_see is set. when the programmed compare match occurs, all operations of the selected compare mode take place. in addition, hardware automatically disables all further compare matches and reset the event enable bit in register ccx_see to 0. as long as this bit is cleared, any compare operation is disabled. to setup a new event, this bit must first be set again. cc1_see single event enable reg. sfr (fe2e h /17 h ) reset value: 0000 h 1514131211109876543210 see 15 see 14 see 13 see 12 see 11 see 10 see 9 see 8 see 7 see 6 see 5 see 4 see 3 see 2 see 1 see 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh cc2_see single event enable reg. sfr (fe2a h /15 h ) reset value: 0000 h 1514131211109876543210 see 15 see 14 see 13 see 12 see 11 see 10 see 9 see 8 see 7 see 6 see 5 see 4 see 3 see 2 see 1 see 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description seey 15 ? 0rw single event enable control 0 single event disabled for channel y 1 single event enabled for channel y note: this bit is cleared by hardware after the event.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-29 v2.2, 2004-01 cc12_x1, v2.1 17.8 staggered and non-staggered operation the capcom units can run in one of two basic operation modes: staggered mode and non-staggered mode. the selection between these modes is performed via register ioc. note: whenever non-staggered mode is enabled (stag = 1) or port lock is activated (pl = 1), the port output registers are not changed by the capcom unit. in staggered mode, a capcom operation cycle consists of 8 module clock cycles, and the outputs of the compare events of the different registers are staggered, that is, the outputs for compare matches with the same compare value are not switched at the same time, but with a fixed time delay. this operation helps to reduce noise and peak power consumption caused by simultaneous switching outputs. in non-staggered mode, a capcom operation cycle is equal to one module clock cycle, and all compare outputs for compare events with the same compare value are switched cc1_ioc i/o control register esfr (f062 h /31 h ) reset value: 0000 h 1514131211109876543210 -- st ag pl - --rwrw- cc2_ioc i/o control register esfr (f066 h /33 h ) reset value: 0000 h 1514131211109876543210 -- st ag pl - --rwrw- field bits type description stag 2rw staggered mode control 0 capcom operates in staggered mode 1 capcom operates in non-staggered mode pl 1rw port lock control 0 compare output signals affect the associated port output latch 1 direct influence of the port output latch by the compare output signals is disabled
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-30 v2.2, 2004-01 cc12_x1, v2.1 in the same clock cycle. this mode offers a faster operation and increased resolution of the capcom unit, 8 times higher than in staggered mode. staggered mode figure 17-12 illustrates the staggered mode operation. in this example, all ccy registers are programmed for compare mode 3. registers cc0, cc1, and cc2 are all programmed for a compare value of fffe h . when the timer increments to fffe h , the comparator detects a match for all of the three registers. the output cc0io of register cc0 is switched to 1 one cycle after the comparator match. however, the outputs cc1io and cc2io are not switched at the same time, but one, respectively two cycles later. this staggering of the outputs continues for all registers including register cc7. the number of the register indicates the delay of the output signal in clock cycles - the output of register cc7 is switched 7 cycles later than the one of register cc0. in the example, the compare value for register cc7 is set to fffd h . thus, the output is switched in the last clock cycle of the capcom cycle in which the timer reached fffd h . when the timer overflows, all compare outputs are reset to 0 (compare mode 3). again, the staggering of the output signals can be seen from figure 17-12 . looking at registers cc8 through cc15 shows that their outputs are switched in parallel to the respective outputs of registers cc0 through cc15. in fact, the staggering is performed in parallel for the upper and the lower register bank. in this way, it is assured, that both compare signals of a register pair in double-register compare mode operate simultaneously. in staggered mode direct port latch switching (see section 17.6 ) is possible. however, it is possible to use the alternate output function option of the associated port pins to output the compare signals.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-31 v2.2, 2004-01 cc12_x1, v2.1 figure 17-12 staggered mode operation mct05428 cc0 = fffe timer contents = fffd timer increments to fffe timer increments to ffff timer is reloaded with fffc timer overflow 1 capcom cycle = 8 f cc clock cycles 1 capcom cycle = 8 f cc clock cycles cc1 = fffe cc2 = fffe cc3 = ffff cc4 = fffe cc5 = ffff cc6 = ffff cc7 = fffd cc8 = fffe cc9 = fffe cc10 = fffe cc11 = ffff cc12 = fffe cc13 = ffff cc14 = ffff cc15 = fffd
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-32 v2.2, 2004-01 cc12_x1, v2.1 non-staggered mode to gain maximum speed and resolution with the capcom unit, it can be switched to non-staggered mode. in this mode, one capcom operation cycle is equal to one module clock cycle. timer increment and the comparison of its new contents with the contents of the compare register takes place within one clock cycle. the appropriate output signals are switched in the following clock cycle (in parallel to the next possible timer increment and comparison). figure 17-13 illustrates the non-staggered mode. note that when the timer overflows, it also takes one additional clock cycle to switch the output signals. note: in non-staggered mode, direct port latch switching is disabled.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-33 v2.2, 2004-01 cc12_x1, v2.1 figure 17-13 non-staggered mode operation mct05429 cc0 = fffe timer contents = fffd timer increments to fffe timer increments to ffff timer is reloaded with fffc timer overflow 1 capcom cycle = 1 f cc clock cycle 1 capcom cycle = 1 f cc clock cycle cc1 = fffe cc2 = fffe cc3 = ffff cc4 = fffe cc5 = ffff cc6 = ffff cc7 = fffd cc8 = fffe cc9 = fffe cc10 = fffe cc11 = ffff cc12 = fffe cc13 = ffff cc14 = ffff cc15 = fffd
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-34 v2.2, 2004-01 cc12_x1, v2.1 17.9 capcom interrupts upon a capture or compare event, the interrupt request flag ccxir for the respective capture/compare register ccx is automatically set. this flag can be used to generate an interrupt or trigger a pec service request when enabled by the interrupt enable bit ccxie. capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred. each of the capture/compare registers has its own bitaddressable interrupt control register and its own interrupt vector allocated. these registers are organized in the same way as all other interrupt control registers. the basic register layout is shown below, table 17-4 lists the associated addresses. note: please refer to the general interrupt control register description for an explanation of the control fields. ccx_ccyic capcom intr. ctrl. reg. (e)sfr ( table 17-4 ) reset value: - - 00 h 1514131211109876543210 -gpx ccy ir ccy ie ilvl glvl - - - - - - - rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-35 v2.2, 2004-01 cc12_x1, v2.1 table 17-4 capcom unit interrupt control register addresses capcom1 unit capcom2 unit register name address reg. space register name address reg. space cc1_cc0ic ff78 h /bc h sfr cc2_cc16ic f160 h /b0 h esfr cc1_cc1ic ff7a h /bd h sfr cc2_cc17ic f162 h /b1 h esfr cc1_cc2ic ff7c h /be h sfr cc2_cc18ic f164 h /b2 h esfr cc1_cc3ic ff7e h /bf h sfr cc2_cc19ic f166 h /b3 h esfr cc1_cc4ic ff80 h /c0 h sfr cc2_cc20ic f168 h /b4 h esfr cc1_cc5ic ff82 h /c1 h sfr cc2_cc21ic f16a h /b5 h esfr cc1_cc6ic ff84 h /c2 h sfr cc2_cc22ic f16c h /b6 h esfr cc1_cc7ic ff86 h /c3 h sfr cc2_cc23ic f16e h /b7 h esfr cc1_cc8ic ff88 h /c4 h sfr cc2_cc24ic f170 h /b8 h esfr cc1_cc9ic ff8a h /c5 h sfr cc2_cc25ic f172 h /b9 h esfr cc1_cc10ic ff8c h /c6 h sfr cc2_cc26ic f174 h /ba h esfr cc1_cc11ic ff8e h /c7 h sfr cc2_cc27ic f176 h /bb h esfr cc1_cc12ic ff90 h /c8 h sfr cc2_cc28ic f178 h /bc h esfr cc1_cc13ic ff92 h /c9 h sfr cc2_cc29ic f184 h /c2 h esfr cc1_cc14ic ff94 h /ca h sfr cc2_cc30ic f18c h /c6 h esfr cc1_cc15ic ff96 h /cb h sfr cc2_cc31ic f194 h /ca h esfr
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-36 v2.2, 2004-01 cc12_x1, v2.1 17.10 external input signal requirements the external input signals of a capcom unit are sampled by the capcom logic based on the module clock and the basic operation mode (staggered or non-staggered mode). to assure that a signal level is recognized correctly, its high or low level must be held active for at least one complete sampling period. the duration of a sampling period is one module clock cycle in non-staggered mode, and 8 module clock cycles in staggered mode. to recognize a signal transition, the signal needs to be sampled twice. if the level of the first sampling is different to the level detected during the second sampling, a transition is recognized. therefore, a minimum of two sampling periods are required for the sampling of an external input signal. thus, the maximum frequency of an input signal must not be higher than half the module clock frequency in non-staggered mode, and a 1/16 th of the module clock frequency in staggered mode. table 17-5 summarizes the requirements and limits for external input signals. in order to use an external signal as a count or capture input, the port pin to which it is connected must be configured as input. note: for example for test purposes a pin used as a count or capture input may be configured as output. software or an other peripheral may control the respective signal and thus trigger count or capture events. in order to cause a compare output signal to be seen by the external world, the associated port pin must be configured as output. compare output signals can either directly switch the port latch, or the output of the ccx_out latch is used as an alternate output function of a port. table 17-5 capcom external input signal limits non-staggered mode staggered mode maximum input frequency f cc /2 f cc /16 minimum input signal level duration 1/ f cc 8/ f cc
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-37 v2.2, 2004-01 cc12_x1, v2.1 17.11 interfaces of the capcom units the capcom units capcom1 (see figure 17-14 ) and capcom2 (see figure 17-15 ) are connected to their environment in different ways. internal connections the overflow/underflow signal t6ouf of gpt2 timer t6 is connected to the capcom units, providing an optional clock source for the capcom timers. the 18 interrupt request lines of each capcom unit are connected to the interrupt control block. note: the input lines from port 2, connected with the capcom1 unit, can also be used as individual external interrupt inputs. external connections the capture/compare signals of both capcom units are connected with input/output ports of the XC161. depending on the selected direction, these ports may provide capture trigger signals from the external system or issue compare output signals to external circuitry. note: capture trigger signals may also be derived from output pins. in this case, software can generate the trigger edges, for example. timers t0 and t7 can be clocked by an external signal. capcom2 ? s timer input signal t7in shares a port pin with capcom1 ? s input/output pin cc15io (see figure 17-15 ). operations in both capcom units can so be combined: the capcom1 compare output can be used to clock capcom2 timer t7, or the capcom2 count input signal can be recorded by a capcom1 capture function.
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-38 v2.2, 2004-01 cc12_x1, v2.1 figure 17-14 capcom1 unit interfaces mca05430 alternate external interrupt input cc14io capcom1 module f cc cc1dis t6ouf interrupt control system control unit (scu) gpt12 unit p6.0/cc0io p6.1/cc1io p6.2/cc2io p6.3/cc3io p6.4/cc4io p6.5/cc5io p6.6/cc6io p6.7/cc7io p3.0/t0in p2.8/cc8io p2.9/cc9io p2.10/cc10io p2.11/cc11io p2.12/cc12io p2.13/cc13io p2.14/cc14io p2.15/t7in/ cc15io cc15irq cc14irq cc13irq cc12irq cc11irq cc10irq cc9irq cc8irq cc7irq cc6irq cc5irq cc4irq cc3irq cc2irq cc1irq cc0irq t1irq t0irq cc15io t0in cc13io cc12io cc11io cc10io cc9io cc8io cc7io cc6io cc5io cc4io cc3io cc2io cc1io cc0io port p3 control port p6 control port p2 control alternate input select external interrupt inputs exnin
XC161 derivatives peripheral units (vol. 2 of 2) capture/compare units user ? s manual 17-39 v2.2, 2004-01 cc12_x1, v2.1 figure 17-15 capcom2 unit interfaces mca05431 cc30io capcom2 module f cc cc2dis t6ouf interrupt control system control unit (scu) gpt12 unit p9.0/cc16io p9.1/cc17io p9.2/cc18io p9.3/cc19io p9.4/cc20io p9.5/cc21io p2.15/t7in/ cc15io p7.4/cc28io p7.5/cc29io p7.6/cc30io cc31irq cc30irq cc29irq cc28irq cc27irq cc26irq cc25irq cc24irq cc23irq cc22irq cc21irq cc20irq cc19irq cc18irq cc17irq cc16irq t8irq t7irq cc31io t7in cc29io cc28io cc21io cc20io cc19io cc18io cc17io cc16io adc injection trigger p1h.0/cc23io p1l.7/cc22io p1h.4/cc24io p1h.5/cc25io p1h.6/cc26io p1h.7/cc27io cc27io cc26io cc25io cc24io cc23io cc22io p7.7/cc31io port p2 control port p9 control port p1 control port p7 control
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-1 v2.2, 2004-01 asc_x, v2.0 18 asynchronous/synchronous serial interface (asc) the XC161 contains two asynchronous/synchronous serial interfaces, asc0 and asc1. the following sections present the general features and operations of such an asc module. the final section describes the actual implementation of the two asc modules including their interconnections with other on-chip modules. the asc supports full-duplex asynchronous communication and half-duplex synchronous communication. the asc provides the following features and functions. features and functions full-duplex asynchronous operating modes ? 8- or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baudrate from 2.5 mbit/s to 50 bit/s (@ 40 mhz module clock f asc ) multiprocessor mode for automatic address/data byte detection loopback capability support for irda data transmission up to 115.2 kbit/s maximum half-duplex 8-bit synchronous operating mode ? baudrate from 5 mbit/s to 202 bit/s (@ 40 mhz module clock f asc ) double buffered transmitter/receiver interrupt generation ? on a transmitter buffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buffer full condition ? on an error condition (frame, parity, overrun error) autobaud detection unit for asynchronous operating modes ? detection of standard baudrates 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, and 230400 bit/s ? detection of non-standard baudrates ? detection of asynchronous modes ? 7 bit, even parity; 7 bit, odd parity; 8 bit, even parity; 8 bit, odd parity; 8 bit, no parity ? automatic initialization of control bits and baudrate generator after detection ? detection of a serial two-byte ascii character frame fifo ? 8-stage receive fifo (rxfifo), 8-stage transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 9-bit fifo data width ? programmable receive/transmit interrupt trigger level ? receive and transmit fifo filling level indication ? overrun and underflow error generation figure 18-1 shows all functional relevant interfaces associated with the asc kernel.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-2 v2.2, 2004-01 asc_x, v2.0 figure 18-1 asc interface diagram asc module (kernel) module bus interface mca05432 port control product interface clock control address decoder interrupt control tir ascxdis abdetir tbir rir eir abstir f asc txd rxd
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-3 v2.2, 2004-01 asc_x, v2.0 18.1 operational overview figure 18-2 shows a block diagram of the asc with its operating modes (asynchronous and synchronous mode). figure 18-2 block diagram of the asc the asc supports full-duplex asynchronous communication with up to 2.5 mbit/s and half-duplex synchronous communication with up to 5 mbit/s (@ 40 mhz module clock). in synchronous mode, data are transmitted or received synchronous to a shift clock that is generated by the microcontroller. in asynchronous mode, either 8- or 9-bit data transfer, parity generation, and the number of stop bits can be selected. parity, framing, and overrun error detection is provided to increase the reliability of data transfers. transmission and reception of data is double-buffered. for multiprocessor communication, a mechanism is provided to distinguish address bytes from data bytes. receive / transmit buffers and shift registers mcb05433 mux serial port control baudrate timer f div prescaler / fractional divider autobaud detection irda decoding f asc rxd irda decoding mux txd asynchronous mode receive / transmit buffers and shift registers serial port control baudrate timer f asc txd rxd rxd shift clock 2 or 3 synchronous mode
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-4 v2.2, 2004-01 asc_x, v2.0 testing is supported by a loop-back option. a 13-bit baudrate timer with a versatile input clock divider circuitry provides the serial clock signal. in a special asynchronous mode, the asc supports irda data transmission up to 115.2 kbit/s with fixed or programmable irda pulse width. autobaud detection allows to detect asynchronous data frames with its baudrate and mode with automatic initialization of the baudrate generator and the mode control bits. a transmission is started by writing to the transmit buffer register tbuf. the selected operating mode determines the number of data bits that will actually be transmitted, so that, bits written to positions 9 through 15 of register tbuf are always insignificant. data transmission is double-buffered, so a new character may be written to the transmit buffer register before the transmission of the previous character is complete. this allows the transmission of characters back-to-back without gaps. data reception is enabled by the receiver enable bit ren. after reception of a character has been completed, the received data can be read from the (read-only) receive buffer register rbuf; the received parity bit can also be read if provided by the selected operating mode. bits in the upper half of rbuf that are not valid in the selected operating mode will be read as zeros. data reception is double-buffered, so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register. in all modes, receive overrun error detection can be selected through bit oen. when enabled, the overrun error status flag oe and the error interrupt request line eir will be activated when the receive buffer register has not been read by the time reception of a ninth character is complete. the previously received character in the receive buffer is overwritten. the loopback mode (selected by bit lb) allows the data currently being transmitted to be received simultaneously in the receive buffer. this may be used to test serial communication routines at an early stage without having to provide an external network. note: in loopback mode, the alternate input/output functions of the associated port pins are not necessary. note: serial data transmission or reception is only possible when the baudrate generator run bit r is set. otherwise, the serial interface is idle. note: do not program the mode control bitfield m to one of the reserved combinations to avoid unpredictable behavior of the serial interface. the operating mode of the serial channel asc is controlled by its control register ascx_con. this register contains control bits for mode and error check selection, and status flags for error identification.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-5 v2.2, 2004-01 asc_x, v2.0 18.2 asynchronous operation asynchronous mode supports full-duplex communication in which both transmitter and receiver use the same data frame format and the same baudrate. data is transmitted on line txd and received on line rxd. irda data transmission/reception is supported up to 115.2 kbit/s. figure 18-3 shows the block diagram of the asc when operating in asynchronous mode. figure 18-3 asynchronous mode of serial channel asc serial port control mca05434 13-bit reload register 13-bit baudrate timer 16 f brt f br f div con.fde mux con.brs fractional divider 2 3 con.r f asc autobaud detection autobaud start int. autobaud detect int. abstir abdetir con.ren con.fen con.pen con.oen con.lb shift clock fifo control shift clock con.oe tir tbir eir receive int. request transmit buffer int. request con.pe con.fe con.stp con.m con.odd rir transmit int. request error int. request receive buffer reg. rbuf transmit buffer reg. tbuf receive shift register transmit shift register irda coding mux sampling mux mux irda decoding internal bus mux 1 txd 1 rxd
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-6 v2.2, 2004-01 asc_x, v2.0 18.2.1 asynchronous data frames 8-bit data frames 8-bit data frames consist of either eight data bits d7 ? d0 (m = 001 b ), or seven data bits d6 ? d0 plus an automatically generated parity bit (m = 011 b ). parity may be odd or even, depending on bit odd. an even parity bit will be set if the modulo-2-sum of the 7 data bits is 1. an odd parity bit will be cleared in this case. parity checking is enabled via bit pen (always off in 8-bit data mode). the parity error flag pe will be set, along with the error interrupt request flag, if a wrong parity bit is received. the parity bit itself will be stored in bit rbuf.7. figure 18-4 asynchronous 8-bit frames mct05435 d0 lsb start bit 0 (2 nd ) stop bit (1 st ) stop bit d1 d2 d3 d4 d5 d6 d7 msb 8 data bits 10-/11-bit uart frame 11 m = 001 b d0 lsb start bit 0 d1 d2 d3 d4 d5 d6 msb parity bit 7 data bits 10-/11-bit uart frame 11 m = 011 b (2 nd ) stop bit (1 st ) stop bit
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-7 v2.2, 2004-01 asc_x, v2.0 9-bit data frames 9-bit data frames consist of either nine data bits d8 ? d0 (m = 100 b ), eight data bits d7 ? d0 plus an automatically generated parity bit (m = 111 b ), or eight data bits d7 ? d0 plus wake-up bit (m = 101 b ). parity may be odd or even, depending on bit odd. an even parity bit will be set if the modulo-2-sum of the 8 data bits is 1. an odd parity bit will be cleared in this case. parity checking is enabled via bit pen (always off in 9-bit data and wake-up mode). the parity error flag pe will be set, along with the error interrupt request flag, if a wrong parity bit is received. the parity bit itself will be stored in bit rbuf.8. figure 18-5 asynchronous 9-bit frames in wake-up mode, received frames are transferred to the receive buffer register only if the 9 th bit (the wake-up bit) is 1. if this bit is 0, no receive interrupt request will be activated and no data will be transferred. this feature may be used to control communication in a multi-processor system: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte to identify the target slave. an address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte, but is a 0 for a data byte; so, no slave will be interrupted by a data ? byte ? . an address ? byte ? will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the eight lsbs of the received character (the address). the addressed slave will switch to 9-bit data mode (such as by clearing bit m[0]), to enable it to also receive the data bytes that will be coming (having the wake-up bit cleared). the slaves not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes. mct05436 d0 lsb start bit 0 (2 nd ) stop bit (1 st ) stop bit d1 d2 d3 d4 d5 d7 bit 9 9 data bits 11-/12-bit uart frame 11 d6 con.m = 100 b : bit 9 = data bit d8 con.m = 101 b : bit 9 = wake-up bit con.m = 111 b : bit 9 = parity bit
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-8 v2.2, 2004-01 asc_x, v2.0 irda frames the modulation schemes of irda are based on standard asynchronous data transmission frames. the asynchronous data format in irda mode (m = 010 b ) is defined as follows: 1 start bit/8 data bits/1 stop bit the coding/decoding of/to the asynchronous data frames is shown in figure 18-6 . in general, during irda transmissions, uart frames are encoded into ir frames and vice versa. a low level on the ir frame indicates an ? led off ? state. a high level on the ir frame indicates an ? led on ? state. for a 0-bit in the uart frame, a high pulse is generated. for a 1-bit in the uart frame, no pulse is generated. the high pulse starts in the middle of a bit cell and has a fixed width of 3/16 of the bit time. the asc also allows the length of the irda high pulse to be programmed. further, the polarity of the received irda pulse can be inverted in irda mode. figure 18-6 shows the non-inverted irda pulse scheme. figure 18-6 irda frame encoding/decoding the asc irda pulse mode/width register pmw contains the 8-bit irda pulse width value and the irda pulse width mode select bit. this register is required in the irda operating mode only. mct05437 0101001101 0101001101 start bit stop bit 8 data bits uart frame start bit stop bit 8 data bits ir frame pulse width = 3/16-bit time (or variable length) bit time 1/2-bit time
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-9 v2.2, 2004-01 asc_x, v2.0 18.2.2 asynchronous transmission asynchronous transmission begins at the next overflow of the divide-by-16 baudrate timer (transition of the baudrate clock f br ), if bit r is set and data has been loaded into tbuf. the transmitted data frame consists of three basic elements: start bit data field (eight or nine bits, lsb first, including a parity bit, if selected) delimiter (one or two stop bits) data transmission is double-buffered. when the transmitter is idle, the transmit data loaded in the transmit buffer register is immediately moved to the transmit shift register, thus freeing the transmit buffer for the next data to be sent. this is indicated by the transmit buffer interrupt request line tbir being activated. tbuf may now be loaded with the next data, while transmission of the previous data continues. the transmit interrupt request line tir will be activated before the last bit of a frame is transmitted, that is, before the first or the second stop bit is shifted out of the transmit shift register. note: the transmitter output pin txd must be configured for alternate data output. 18.2.3 transmit fifo operation the transmit fifo (txfifo) provides the following functionality: enable/disable control programmable filling level for transmit interrupt generation filling level indication fifo clear (flush) operation fifo overflow error generation the 8-stage transmit fifo is controlled by the txfcon control register. when bit txfen is set, the transmit fifo is enabled. the interrupt trigger level defined by txfitl defines the filling level of the txfifo at which a transmit buffer interrupt tbir or a transmit interrupt tir is generated. these interrupts are always generated when the filling level of the transmit fifo is equal to or less than the value stored in txfitl. bitfield txffl in the fifo status register ascx_fstat indicates the number of entries that are actually written (valid) in the txfifo. therefore, the software can verify, in the interrupt service routine, for instance, how many bytes can still be written into the transmit fifo via register tbuf without getting an overrun error. the transmit fifo cannot be accessed directly. all data write operations into the txfifo are executed by writing into the tbuf register.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-10 v2.2, 2004-01 asc_x, v2.0 figure 18-7 transmit fifo operation example the example in figure 18-7 shows a typical 8-stage transmit fifo operation. in this example seven bytes are transmitted via the txd output line. the transmit fifo interrupt trigger level txfitl is set to 0011 b . the first byte written into the empty txfifo via tbuf is directly transferred into the transmit shift register and is not written into the fifo. a transmit buffer interrupt will be generated in this case. after byte 1, bytes 2 to 6 are written into the transmit fifo. after the transfer of byte 3 from the txfifo into the transmit shift register of the asc, 3 bytes remain in the txfifo. therefore, the value of txfitl is reached and a transmit buffer interrupt will be generated at the beginning and a transmit interrupt at the end of the byte 3 serial transmission. during the serial transmission of byte 4, another byte (byte 7) is written into the txfifo (tbuf write operation). finally, after the start of the serial transmission of byte 7, the txfifo is again empty. mct05438 byte 6 byte 5 byte 4 byte 3 0101 byte 2 tbir 0100 byte 3 tir tbir 0011 tir tbir 0010 byte 5 tir tbir 0010 byte 7 byte 6 tir tir tbir 0001 0000 0000 txd fstat. txffl byte 6 byte 5 byte 4 byte 6 byte 5 byte 6 byte 5 byte 7 byte 6 byte 7 byte 7 txfifo empty byte 6 byte 5 byte 4 byte 3 byte 2 byte 5 byte 4 byte 3 byte 2 byte 4 byte 3 byte 2 byte 3 byte 2 byte 2 writing byte 1 writing byte 2 writing byte 3 writing byte 4 writing byte 5 writing byte 6 writing byte 7 txfcon.txfitl = 0011 b byte 1 byte 4 tbir
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-11 v2.2, 2004-01 asc_x, v2.0 if the txfifo is full and additional bytes are written into tbuf, the error interrupt will be generated with bit oe set. in this case, the data byte that was last written into the transmit fifo is overwritten and the transmit fifo filling level txffl is set to maximum. the txfifo can be flushed or cleared by setting bit txfflu in register ascx_txfcon. after this txfifo flush operation, the txfifo is empty and the transmit fifo filling level txffl is set to 0000 b . a running serial transmission is not aborted by a receive fifo flush operation note: the txfifo is flushed automatically with a reset operation of the asc module and if the txfifo becomes disabled (resetting bit txfen) after it was previously enabled.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-12 v2.2, 2004-01 asc_x, v2.0 18.2.4 asynchronous reception asynchronous reception is initiated by a falling edge (1-to-0 transition) on line rxd, provided that bits r and ren are set. the receive data input line rxd is sampled at 16 times the rate of the selected baudrate. a majority decision of the 7 th , 8 th , and 9 th sample determines the effective bit value. this avoids erroneous results that may be caused by noise. if the detected value is not a 0 when the start bit is sampled, the receive circuit is reset and waits for the next 1-to-0 transition at line rxd. if the start bit proves valid, the receive circuit continues sampling and shifts the incoming data frame into the receive shift register. when the last stop bit has been received, the content of the receive shift register are transferred to the receive data buffer register rbuf. simultaneously, the receive interrupt request line rir is activated after the 9 th sample in the last stop bit time slot (as programmed), regardless of whether valid stop bits have been received or not. the receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input line. note: the receiver input pin rxd must be configured for input. asynchronous reception is stopped by clearing bit ren. a currently received frame is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. start bits that follow this frame will not be recognized. note: in wake-up mode, received frames are transferred to the receive buffer register only if the 9 th bit (the wake-up bit) is 1. if this bit is 0, no receive interrupt request will be activated and no data will be transferred. 18.2.5 receive fifo operation the receive fifo (rxfifo) provides the following functionality: enable/disable control programmable filling level for receive interrupt generation filling level indication fifo clear (flush) operation fifo overflow error generation the 8-stage receive fifo is controlled by the rxfcon control register. when bit rxfen is set, the receive fifo is enabled. the interrupt trigger level defined by rxfitl defines the filling level of rxfifo at which a receive interrupt rir is generated. rir is always generated when the filling level of the receive fifo is equal to or greater than the value stored in rxfitl. bitfield rxffl in the fifo status register ascx_fstat indicates the number of bytes that have been actually written into the fifo and can be read out of the fifo by a user program.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-13 v2.2, 2004-01 asc_x, v2.0 the receive fifo cannot be accessed directly. all data read operations from the rxfifo are executed by reading the rbuf register. figure 18-8 receive fifo operation example the example in figure 18-8 shows a typical 8-stage receive fifo operation. in this example, six bytes are received via the rxd input line. the receive fifo interrupt trigger level rxfitl is set to 0011 b . therefore, the first receive interrupt rir is generated after the reception of byte 3 (rxfifo is filled with three bytes). after the reception of byte 4, three bytes are read out of the receive fifo. after this read operation, the rxfifo still contains one byte. rir becomes again active after two more bytes (byte 5 and 6) have been received (rxfifo filled again with 3 bytes). finally, the fifo is cleared after three read operation. if the rxfifo is full and additional bytes are received, the receive interrupt rir and the error interrupt eir will be generated with bit oe set. in this case, the data byte last written into the receive fifo is overwritten. with the overrun condition, the receive fifo filling level rxffl is set to maximum. if a rbuf read operation is executed with the rxfifo mct05439 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 0000 0001 0010 0011 0100 0001 0010 0100 0000 byte 1 byte 1 byte 2 byte 1 byte 2 byte 3 byte 1 byte 2 byte 3 byte 4 byte 4 byte 4 byte 5 byte 6 rxfifo empty rir rir rir read rbuf (byte 1) read rbuf (byte 2) read rbuf (byte 3) read rbuf (byte 4) read rbuf (byte 5) read rbuf (byte 6) rxd content of fstat.rxffl rxfcon.rxfitl = 0011 b byte 4 byte 5
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-14 v2.2, 2004-01 asc_x, v2.0 enabled but empty, an error interrupt eir will be generated as well with bit oe set. in this case, the receive fifo filling level rxffl is set to 0000 b . if the rxfifo is available but disabled (rxfen = 0) and the receive operation is enabled (ren = 1), the asynchronous receive operation is functionally equivalent to the asynchronous receive operation of the asc module. the rxfifo can be flushed or cleared by setting bit rxfflu in register rxfcon. after this rxfifo flush operation, the rxfifo is empty and the receive fifo filling level rxffl is set to 0000 b . the rxfifo is flushed automatically with a reset operation of the asc module and if the rxfifo becomes disabled (resetting bit rxfen) after it was previously enabled. resetting bit ren without resetting rxfen does not affect (reset) the rxfifo state. this means that the receive operation of the asc is stopped, in this case, without changing the content of the rxfifo. after setting ren again, the rxfifo with its content is again available. note: after a successful autobaud detection sequence (if implemented), the rxfifo should be flushed before data is received.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-15 v2.2, 2004-01 asc_x, v2.0 18.2.6 fifo transparent mode in transparent mode, a specific interrupt generation mechanism is used for receive and transmit buffer interrupts. in general, in transparent mode, receive interrupts are always generated if data bytes are available in the rxfifo. transmit buffer interrupts are always generated if the txfifo is not full. the relevant conditions for interrupt generation in transparent mode are: fifo filling levels read/write operations on the rbuf/tbuf data register interrupt generation for the receive fifo depends on the rxfifo filling level and the execution of read operations of register rbuf (see figure 18-9 ). transparent mode for the rxfifo is enabled when bits rxtmen and rxfen in register ascx_rxfcon are set. figure 18-9 transparent mode receive fifo operation if the rxfifo is empty, a receive interrupt rir is always generated when the first byte is written into an empty rxfifo (rxffl changes from 0000 b to 0001 b ). if the rxfifo is filled with at least one byte, the occurrence of further receive interrupts depends on the read operations of register rbuf. the receive interrupt rir will always be activated after a rbuf read operation if the rxfifo still contains data (rxffl is not equal to 0000 b ). if the rxfifo is empty after a rbuf read operation, no further receive interrupt will be generated. if the rxfifo is full (rxffl = maximum) and additional bytes are received, an error interrupt eir will be generated with bit oe set. in this case, the data byte last written into the receive fifo is overwritten. if a rbuf read operation is executed with the rxfifo enabled but empty (underflow condition), an error interrupt eir will be generated as well, with bit oe set. if the rxfifo is flushed in transparent mode, the software must take care that a previous pending receive interrupt is ignored. mct05440 byte 1 byte 2 byte 3 byte 4 0000 0001 0010 0011 0100 rxd rir (1) content of rxfcon. rxffl 0011 0010 0001 0001 read rbuf rir (2) rir (3) rir (4) read byte 1 read byte 2 read byte 3 read byte 4
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-16 v2.2, 2004-01 asc_x, v2.0 note: the receive fifo interrupt trigger level bitfield rxfitl is a don ? t care in transparent mode. interrupt generation for the transmit fifo depends on the txfifo filling level and the execution of write operations to the register tbuf. transparent mode for the txfifo is enabled when bits txtmen and txfen are set. a transmit buffer interrupt tbir is always generated when the txfifo is not full (txffl not equal to maximum) after a byte has been written into register ascx_tbuf. tbir is also activated after a txfifo flush operation or when the txfifo becomes enabled (txtmen and txfen set) when it was previously disabled. in these cases, the txfifo is empty and ready to be filled with data. if the txfifo is full (txffl = maximum) and an additional byte is written into tbuf, no further transmit buffer interrupt will be generated after the tbuf write operation. in this case the data byte last written into the transmit fifo is overwritten and an overrun error interrupt (eir) will be generated with bit oe set. note: the transmit fifo interrupt trigger level bitfield txfitl is a don ? t care in transparent mode. 18.2.7 irda mode the duration of the irda pulse is normally 3/16 of a bit period. the irda standard also allows the pulse duration to be independent of the baudrate or bit period. in this case, the width of the transmitted pulse always corresponds to the 3/16 pulse width at 115.2 kbit/s, which is 1.627 s. either fixed or bit-period-dependent irda pulse width generation can be selected. the irda pulse width mode is selected by bit irpw. in case of fixed irda pulse width generation, the lower eight bits in register pmw are used to adapt the irda pulse width to a fixed value such as 1.627 s. the fixed irda pulse width is generated by a programmable timer as shown in figure 18-10 . figure 18-10 fixed irda pulse generation the irda pulse width can be calculated according the formulas given in table 18-1 . note: the name pmw in the formulas of table 18-1 represents the contents of the pulse mode/width register pmw (pw_value), taken as an unsigned 8-bit integer. mca05441 pwm 8-bit timer f asc irda pulse start timer t ipw
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-17 v2.2, 2004-01 asc_x, v2.0 the contents of pw_value further define the minimum irda pulse width ( t ipw min ) that is still recognized as a valid irda pulse during a receive operation. this function is independent of the selected irda pulse width mode (fixed or variable) which is defined by bit irpw. the minimum irda pulse width is calculated by a shift right operation of pmw bit 7-0 by one bit divided by the module clock f asc . note: if irpw is cleared (fixed irda pulse width), pw_value must be a value which assures that t ipw > t ipw min . table 18-2 gives three examples for typical frequencies of f asc . 18.2.8 rxd/txd data path selection in asynchronous modes the data paths for the serial input and output data in asynchronous mode are affected by several control bits in the registers con and abcon as shown in figure 18-11 . the synchronous mode operation is not affected by these data path selection capabilities. the input signal from rxd passes an inverter which is controlled by bit rxinv. the output signal of this inverter is used for the autobaud detection and may bypass the logic in the echo mode (controlled by bit abem). further, two multiplexers are in the rxd input signal path for providing the loopback mode capability (controlled by bit lb) and the irda receive pulse inversion capability (controlled by bit rxdi). depending on the asynchronous mode (controlled by bitfield m), output signal or the rxd input signal in echo mode (controlled by bit abem) is switched to the txd output via an inverter (controlled by bit txinv). table 18-1 formulas for irda pulse width calculation pmw pmw_ipmw formulas 1 ? 255 0 1 table 18-2 irda pulse width adaption to 1.627 s f asc pmw t ipw error t ipw min 20 mhz 33 1.65 s -1.1% 0.8 s 50 mhz 81 1.62 s -1.0% 0.8 s 66 mhz 107 1.621 s -1.0% 0.81 s t ipw 3 16 baudrate --------------------------------------- = t ipw min pmw >> 1 () f asc -------------------------------- - = t ipw pmw f asc -------------- - =
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-18 v2.2, 2004-01 asc_x, v2.0 figure 18-11 rxd/txd data path in asynchronous modes note: in echo mode the transmit output signal is blocked by the echo mode output multiplexer. figure 18-11 shows that it is not possible to use an irda coded receiver input signal for autobaud detection. asc asynch. mode logic mca05442 irda coding irda decode con mux mux mux rxd mux mux autobaud detection abcon rxdi lb m mux txd rxinv txinv abem
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-19 v2.2, 2004-01 asc_x, v2.0 18.3 synchronous operation synchronous mode supports half-duplex communication, basically for simple i/o expansion via shift registers. data is transmitted and received via line rxd while line txd outputs the shift clock. synchronous mode is selected with bitfield m = 000 b . eight data bits are transmitted or received synchronous to a shift clock generated by the internal baudrate generator. the shift clock is active only as long as data bits are transmitted or received. figure 18-12 synchronous mode of serial channel asc serial port control mca05443 13-bit reload register 13-bit baudrate timer f brt f br f div mux 2 3 r f asc shift clock fifo control shift clock tir tbir eir receive int. request transmit buffer int. request m = 000 b rir transmit int. request error int. request receive fifo reg. rbuf transmit fifo reg. tbuf receive shift register transmit shift register mux internal bus brs oe ren oen lb rxd txd 4 0 1
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-20 v2.2, 2004-01 asc_x, v2.0 18.3.1 synchronous transmission synchronous transmission begins within four state times after data has been loaded into tbuf, provided that bit r is set and bit ren is cleared (half-duplex, no reception). exception: in loopback mode (bit lb set), ren must be set for reception of the transmitted byte. data transmission is double-buffered. when the transmitter is idle, the transmit data loaded into tbuf is immediately moved to the transmit shift register, thus freeing tbuf for more data. this is indicated by the transmit buffer interrupt request line tbir being activated. tbuf may now be loaded with the next data, while transmission of the previous continuous. the data bits are transmitted synchronous with the shift clock. after the bit time for the eighth data bit, both the txd and rxd lines will go high, the transmit interrupt request line tir is activated, and serial data transmission stops. note: pin txd must be configured for alternate data output in order to provide the shift clock. pin rxd must also be configured for output during transmission. 18.3.2 synchronous reception synchronous reception is initiated by setting bit ren. if bit r is set, the data applied at rxd is clocked into the receive shift register synchronous to the clock that is output at txd. after the eighth bit has been shifted in, the contents of the receive shift register are transferred to the receive data buffer rbuf, the receive interrupt request line rir is activated, the receiver enable bit ren is reset, and serial data reception stops. note: pin txd must be configured for alternate data output in order to provide the shift clock. pin rxd must be configured as alternate data input. synchronous reception is stopped by clearing bit ren. a currently received byte is completed, including the generation of the receive interrupt request and an error interrupt request, if appropriate. writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission. if a previously received byte has not been read out of a full receive buffer at the time the reception of the next byte is complete, both the error interrupt request line eir and the overrun error status flag oe will be activated/set, provided the overrun check has been enabled by bit oen. 18.3.3 synchronous timing figure 18-13 shows timing diagrams of the asc synchronous mode data reception and data transmission. in idle state, the shift clock level is high. with the beginning of a synchronous transmission of a data byte, the data is shifted out at rxd with the falling edge of the shift clock. if a data byte is received through rxd, data is latched with the rising edge of the shift clock. between two consecutive receive or transmit data bytes, one shift clock cycle ( f br ) delay is inserted.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-21 v2.2, 2004-01 asc_x, v2.0 figure 18-13 asc synchronous mode waveforms mct05444 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 shift clock (txd) transmit data (rxd) receive data (rxd) continuous transmit timing 1. byte 2. byte 1. byte 2. byte valid data n + 1 valid data n + 2 valid data n data bit n + 1 data bit n + 2 data bit n latch shift shift shift shift clock (txd) transmit data (rxd) receive data (rxd) receive/transmit timing
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-22 v2.2, 2004-01 asc_x, v2.0 18.4 baudrate generation the serial channel asc has its own dedicated 13-bit baudrate generator with reload capability, allowing baudrate generation independent of other timers. the baudrate generator is clocked with a clock ( f div ) derived via a prescaler from the asc input clock f asc . the baudrate timer counts downwards and can be started or stopped through the baudrate generator run bit r. each underflow of the timer provides one clock pulse to the serial channel. the timer is reloaded with the value stored in its 13-bit reload register each time it underflow. the resulting clock f brt is again divided by a factor for the baudrate clock (16 in asynchronous modes and 4 in synchronous mode). the prescaler is selected by the bits brs and fde. in addition to the two fixed dividers, a fractional divider prescaler unit is available in the asynchronous modes that allows selection of prescaler divider ratios of n/512 with n = 0 ? 511. therefore, the baudrate of asc is determined by the module clock, the content of fdv, the reload value of bg, and the operating mode (asynchronous or synchronous). register ascx_bg is the dual-function baudrate generator/reload register. reading ascx_bg returns the contents of the timer br_value (bits 15 ? 13 return zero), while writing to bg always updates the reload register (bits 15 ? 13 are insignificant). an autoreload of the timer with the contents of the reload register is performed each time ascx_bg is written to. however, if bit r is cleared at the time a write operation to ascx_bg is performed, the timer will not be reloaded until the first instruction cycle after bit r was set. for a clean baudrate initialization, ascx_bg should be written only if r = 0. if ascx_bg is written while r = 1, unpredictable behavior of the asc may occur during running transmit or receive operations. the asc baudrate timer reload register ascx_bg contains the 13-bit reload value for the baudrate timer in asynchronous and synchronous modes. 18.4.1 baudrate in asynchronous mode for asynchronous mode, the baudrate generator provides a clock f brt with sixteen times the rate of the established baudrate. every received bit is sampled at the 7 th , 8 th , and 9 th cycle of this clock. the clock divider circuitry, which generates the input clock for the 13-bit baudrate timer, is extended by a fractional divider circuitry that allows adjustment for more accurate baudrate and the extension of the baudrate range. the baudrate of the baudrate generator depends on the following bits and register values: input clock f asc selection of the baudrate timer input clock f div by bits fde and brs if bit fde is set (fractional divider): value of register ascx_fdv value of the 13-bit reload register ascx_bg
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-23 v2.2, 2004-01 asc_x, v2.0 the output clock of the baudrate timer with the reload register is the sample clock in the asynchronous modes of the asc. for baudrate calculations, this baudrate clock f br is derived from the sample clock f div by a division by 16. the asc fractional divider register ascx_fdv contains the 9-bit divider value for the fractional divider (asynchronous mode only). it is also used for reference clock generation of the autobaud detection unit. figure 18-14 asc baudrate generator circuitry in asynchronous modes using the fixed input clock divider the baudrate for asynchronous operation of serial channel asc when using the fixed input clock divider ratios (fde = 0) and the required reload value for a given baudrate can be determined by the following formulas: bg represents the contents of the reload bitfield br_value, taken as unsigned 13-bit integer. the maximum baudrate that can be achieved for the asynchronous modes when using the two fixed clock divider and a module clock of 40 mhz is 1.25 mbit/s. table 18-4 lists various commonly used baudrates together with the required reload values and the deviation errors compared to the intended baudrate. note: fde must be 0 to achieve the baudrates in table 18-3 . the deviation errors given in the table are rounded. using a baudrate crystal will provide correct baudrates without deviation errors. mca05445 13-bit reload register 13-bit baudrate timer 16 f brt f br f div mux fractional divider 2 3 r f asc brs fde baudrate clock sample clock brs 0 1 x selected divider 2 3 fractional divider fde 0 0 1
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-24 v2.2, 2004-01 asc_x, v2.0 using the fractional divider when the fractional divider is selected, the input clock f div for the baudrate timer is derived from the module clock f asc by a programmable divider. if bit fde is set, the fractional divider is activated. it divides f asc by a fraction of n/512 for any value of n from 0 to 511. if n = 0, the divider ratio is 1, which means that f div = f asc . in general, the fractional divider allows the baudrate to be programmed with much more accuracy than with the two fixed prescaler divider stages. note: bg represents the contents of the reload bitfield br_value, taken as an unsigned 13-bit integer. note: fdv represents the contents of the fractional divider register fd_value taken as an unsigned 9-bit integer. table 18-3 asynchronous baudrate formulas using the fixed input clock dividers fde brs bg formula 000 ? 8191 1 table 18-4 typical asynchronous baudrates using the fixed input clock dividers baudrate brs = 0, f asc = 40 mhz brs = 1, f asc = 40 mhz deviation error reload value deviation error reload value 1.25 mbit/s --- 0000 h na na 19.2 kbit/s +0.1% / -1.3% 0040 h / 0041 h +0.9% / -1.3% 002a h / 002b h 9600 bit/s +0.1% / -0.6% 0081 h / 0082 h +0.9% / -0.2% 0055 h / 0056 h 4800 bit/s +0.1% / -0.2% 0103 h / 0104 h +0.3% / -0.2% 00ac h / 00ad h 2400 bit/s +0.1% / -0.0% 0207 h / 0208 h +0.0% / -0.2% 015a h / 015b h 1200 bit/s +0.0% / -0.0% 0410 h / 0411 h +0.0% / -0.0% 02b5 h / 02b6 h baudrate f asc 32 bg 1 + () ------------------------------------ = bg f asc 32 baudrate --------------------------------------- 1 ? = baudrate f asc 48 bg 1 + () ------------------------------------ = bg f asc 48 baudrate --------------------------------------- 1 ? =
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-25 v2.2, 2004-01 asc_x, v2.0 table 18-5 async. baudrate formulas using the fractional input clock divider fde brs bg fdv formula 1 ? 1 ? 8191 1 ? 511 0 table 18-6 typical asynchronous baudrates using the fractional input clock divider f asc desired baudrate bg fdv resulting baudrate deviation 40 mhz 115.2 kbit/s 04 h 076 h 115.234 kbit/s 0.02% 57.6 kbit/s 04 h 03b h 57.617 kbit/s 0.02% 38.4 kbit/s 0e h 076 h 38.411 kbit/s 0.02% 19.2 kbit/s 0e h 03b h 19.206 kbit/s 0.02% baudrate fdv 512 ------------ f asc 16 bg 1 + () ------------------------------------ = baudrate f asc 16 bg 1 + () ------------------------------------ =
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-26 v2.2, 2004-01 asc_x, v2.0 18.4.2 baudrate in synchronous mode for synchronous operation, the baudrate generator provides a clock with four times the rate of the established baudrate (see figure 18-15 ). figure 18-15 asc baudrate generator circuitry in synchronous mode the baudrate for synchronous operation of serial channel asc can be determined by the formulas as shown in table 18-7 . note: bg represents the contents of the reload bitfield br_value, taken as an unsigned 13-bit integers. the maximum baudrate that can be achieved in synchronous mode when using a module clock of 40 mhz is 5 mbit/s. table 18-7 synchronous baudrate formulas brs bg formula 00 ? 8191 1 mca05446 13-bit reload register 13-bit baudrate timer f brt f div mux 2 3 r f asc brs shift / sample clock selected divider 2 3 brs 0 1 4 baudrate f asc 8bg1 + () -------------------------------- - =bg f asc 8baudrate ------------------------------------ 1 ? = baudrate f asc 12 bg 1 + () ------------------------------------ =bg f asc 12 baudrate --------------------------------------- 1 ? =
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-27 v2.2, 2004-01 asc_x, v2.0 18.5 autobaud detection 18.5.1 general operation autobaud detection provides a capability to recognize the mode and the baudrate of an asynchronous input signal at rxd. generally, the baudrates to be recognized must be known by the application. with this knowledge always a set of nine baudrates can be detected. the autobaud detection is not designed to calculate a baudrate of an unknown asynchronous frame. figure 18-16 shows how the autobaud detection is integrated into its asynchronous mode configuration. the rxd data line is an input to the autobaud detection unit. the clock f div , generated by the fractional divider, is used by the autobaud detection unit as time base. after successful recognition of baudrate and asynchronous mode of the rxd data input signal, bits in register ascx_con and the value of register ascx_bg in the baudrate timer are set to the appropriate values, and the asc can start immediately with the reception of serial input data. figure 18-16 asynchronous mode block diagram note: autobaud detection is not available in synchronous mode. the following sequence must be executed to start the autobaud detection unit: definition of the baudrates to be detected: standard or non-standard baudrates programming of the prescaler/fractional divider to select a specific value of f div starting the prescaler/fractional divider (setting bit r) preparing the interrupt system enabling the autobaud detection (setting bit en and the interrupt enable bits in abcon for interrupt generation, if required) polling interrupt request flag or waiting for the autobaud detection interrupt receive / transmit buffers and shift registers mca05447 mux serial port control baudrate timer f div prescaler / fractional divider autobaud detection irda decoding f asc rxd irda decoding mux txd asynchronous mode
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-28 v2.2, 2004-01 asc_x, v2.0 18.5.2 serial frames for autobaud detection the autobaud detection is based on the serial reception of a specific two-byte serial frame. this serial frame is build up by the two ascii bytes ? at ? or ? at ? ( ? at ? or ? at ? are not allowed). both byte combinations can be detected in five types of asynchronous frames. figure 18-17 and figure 18-18 show the serial frames which are detected at least. note: some other two-byte combinations will be defined too. figure 18-17 two-byte serial frames with ascii ? at ? mct05448 100001111 001011101 ?a? = 61 h 7 bit, even parity start ?t? = 74 h 100001101 001011111 ?a? = 61 h 7 bit, odd parity ?t? = 74 h 100001101 001011101 ?a? = 61 h 8 bit, no parity ?t? = 74 h 100001101 001011100 ?a? = 61 h 8 bit, even parity ?t? = 74 h 11 100001100 001011101 ?a? = 61 h 8 bit, odd parity ?t? = 74 h 11 parity stop start parity stop start parity stop start parity stop start stop start stop start parity stop start parity stop parity stop start parity stop start
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-29 v2.2, 2004-01 asc_x, v2.0 figure 18-18 two-byte serial frames with ascii ? at ? 18.5.3 baudrate selection and calculation autobaud detection requires some calculations concerning the programming of the baudrate generator and the baudrates to be detected. two steps must be considered: defining the baudrate(s) to be detected programming of the baudrate timer prescaler - setup of the clock rate of f div mct05449 100000101 001010111 ?a? = 41 h 7 bit, even parity ?t? = 54 h 100000111 001010101 ?a? = 41 h 7 bit, odd parity ?t? = 54 h 100000101 001010101 ?a? = 41 h 8 bit, no parity ?t? = 54 h 100000100 001010101 ?a? = 41 h 8 bit, even parity ?t? = 54 h 11 100000101 001010100 ?a? = 41 h 8 bit, odd parity ?t? = 54 h 11 start parity stop start parity stop start parity stop start parity stop start stop start stop start parity stop start parity stop start parity stop start parity stop
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-30 v2.2, 2004-01 asc_x, v2.0 in general, the baudrate generator in asynchronous mode is build up by two parts (see also figure 18-14 ): the clock prescaler part which derives f div from f asc the baudrate timer part which generates the sample clock f brt and the baudrate clock f br prior to an autobaud detection the prescaler part has to be set up by the cpu while the baudrate timer (register ascx_bg) is initialized with a 13-bit value (br_value) automatically after a successful autobaud detection. for the following calculations, the fractional divider is used (fde = 1). note: it is also possible to use the fixed divide-by-2 or divide-by-3 prescaler. but the fractional divider allows the much more precise adaption of f div to the required value. standard baudrates for standard baudrate detection the baudrates as shown in table 18-8 can be e.g. detected. therefore, the output frequency f div of the baudrate generator must be set to a frequency derived from the module clock f asc in a way that it is equal to 11.0592 mhz. the value to be written into register fdv is the nearest integer value which is calculated according the following formula: (18.1) table 18-8 defines the nine standard baudrates (br0 - br8) which can be detected for f div = 11.0592 mhz. table 18-8 autobaud detection using standard baudrates ( f div = 11.0592 mhz) baudrate numbering detectable standard baudrate divide factor d f bg is loaded after detection with value br0 230.400 kbit/s 48 2 = 002 h br1 115.200 kbit/s 96 5 = 005 h br2 57.600 kbit/s 192 11 = 00b h br3 38.400 kbit/s 288 17 = 011 h br4 19.200 kbit/s 576 35 = 023 h br5 9600 bit/s 1152 71 = 047 h br6 4800 bit/s 2304 143 = 08f h br7 2400 bit/s 4608 287 = 11f h br8 1200 bit/s 9216 575 = 23f h fdv 512 11.0592 mhz f asc --------------------------------------------------- - =
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-31 v2.2, 2004-01 asc_x, v2.0 according to table 18-8 a baudrate of 9600 bit/s is achieved when register ascx_bg is loaded with a value of 047 h , assuming that f div has been set to 11.0592 mhz. table 18-8 also lists a divide factor d f which is defined with the following formula: (18.2) this divide factor d f defines a fixed relationship between the prescaler output frequency f div and the baudrate to be detected during the autobaud detection operation. this means, changing f div results in a totally different baudrate table in means of baudrate values. for the baudrates to be detected, the following relations are always valid: br0 = f div /48 d , br1 = f div /96 d , ? up to br8 = f div /9216 d a requirement for detecting standard baudrates up to 230.400 kbit/s is the f div minimum value of 11.0592 mhz. with the value fd_value the fractional divider f div is adapted to the module clock frequency f asc . table 18-9 defines the deviation of the standard baudrates when using autobaud detection depending on the module clock f asc . note: if the deviation of the baudrate after autobaud detection is to high, the baudrate generator (fractional divider fdv and reload register ascx_bg) can be reprogrammed if required to get a more precise baudrate with less error. table 18-9 standard baudrates - deviations and errors for autobaud detection f asc fdv error in f div 10 mhz not possible 12 mhz 472 +0.03% 13 mhz 436 +0.1% 16 mhz 354 +0.03% 18 mhz 315 +0.14% 18.432 mhz 307 -0.07% 20 mhz 283 -0.04% 24 mhz 236 +0.03% 25 mhz 226 -0.22% 30 mhz 189 +0.14% 33 mhz 172 +0.24% 40 mhz 142 +0.31% baudrate f div d f -------- - =
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-32 v2.2, 2004-01 asc_x, v2.0 non-standard baudrates due to the relationship between br0 to br8 in table 18-8 concerning the divide factor d f other baudrates than the standard baudrates can be also selected. e.g. if a baudrate of 50 kbit/s has to be detected, br2 is e.g. defined as baudrate for the 50 kbit/s selection. this further results in: f div = 50 kbit/s d f @br2 = 50 kbit/s 192 = 9.6 mhz therefore, depending on the module clock frequency f asc , the value of the fractional divider (register fdv must be set in this example according to the formula: with f div = 9.6 mhz (18.3) using this selection ( f div = 9.6 mhz), the detectable baudrates start at 200 kbit/s (br0) down to 1042 bit/s (br8). table 18-10 shows the baudrate table for this example. table 18-10 autobaud detection using non-standard baudrates ( f div = 9.6 mhz) baudrate numbering detectable non- standard baudrates divide factor d f bg is loaded after detection with value br0 200.000 kbit/s 48 2 = 002 h br1 100.000 kbit/s 96 5 = 005 h br2 50 kbit/s 192 11 = 00b h br3 33.333 kbit/s 288 17 = 011 h br4 16.667 kbit/s 576 35 = 023 h br5 8333 bit/s 1152 71 = 047 h br6 4167 bit/s 2304 143 = 08f h br7 2083 bit/s 4608 287 = 11f h br8 1047 bit/s 9216 575 = 23f h fdv 512 f div f asc ------------------------- =
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-33 v2.2, 2004-01 asc_x, v2.0 18.5.4 overwriting registers on successful autobaud detection with a successful autobaud detection some bits in registers ascx_con and ascx_bg are automatically set to a value which corresponds to the mode and baudrate of the detected serial frame conditions (see table 18-11 ). in control register ascx_con the mode control bits m and the parity select bit odd are overwritten. register ascx_bg is loaded with the 13-bit reload value for the baudrate timer. note: the autobaud detection interrupts are described in section 18.7 . table 18-11 autobaud detection overwrite values for the con register detected parameters m odd br_value operating mode 7 bit, even parity 7 bit, odd parity 8 bit, even parity 8 bit, odd parity 8 bit, no parity 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 ? baudrate br0 br1 br2 br3 br4 br5 br6 br7 br8 ?? 2 = 002 h 5 = 005 h 11 = 00b h 17 = 011 h 35 = 023 h 71 = 047 h 143 = 08f h 287 = 11f h 575 = 23f h
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-34 v2.2, 2004-01 asc_x, v2.0 18.6 hardware error detection capabilities to improve the safety of serial data exchange, the serial channel asc provides an error interrupt request flag to indicate the presence of an error, and three (selectable) error status flags in register ascx_con to indicate which error has been detected during reception. upon completion of a reception, the error interrupt request line eir will be activated simultaneously with the receive interrupt request line rir, if one or more of the following conditions are met: if the framing error detection enable bit fen is set and any of the expected stop bits is not high, the framing error flag fe is set, indicating that the error interrupt request is due to a framing error (asynchronous mode only). if the parity error detection enable bit pen is set in the modes where a parity bit is received, and the parity check on the received data bits proves false, the parity error flag pe is set, indicating that the error interrupt request is due to a parity error (asynchronous mode only). if the overrun error detection enable bit oen is set and the last character received was not read out of the receive buffer by software or by a dma transfer at the time the reception of a new frame is complete, the overrun error flag oe is set indicating that the error interrupt request is due to an overrun error (asynchronous and synchronous mode).
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-35 v2.2, 2004-01 asc_x, v2.0 18.7 interrupts six interrupt sources are provided for serial channel asc. line tir indicates a transmit interrupt, tbir indicates a transmit buffer interrupt, rir indicates a receive interrupt and eir indicates an error interrupt of the serial channel. the autobaud detection unit provides two additional interrupts, the abstir start of autobaud operation interrupt and the abdetir autobaud detected interrupt. the interrupt output lines tbir, tir, rir, eir, abstir, and abdetir are activated (active state) for two periods of the module clock f asc . the cause of an error interrupt request (framing, parity, overrun error) can be identified by the error status flags fe, pe, and oe. for the two autobaud detection interrupts register abstat provides status information. note: in contrary to the error interrupt request line eir, the error status flags fe/pe/oe are not reset automatically but must be cleared by software. for normal operation (i.e. besides the error interrupt) the asc provides three interrupt requests to control data exchange via this serial channel: tbir is activated when data is moved from tbuf to the transmit shift register. tir is activated before the last bit of an asynchronous frame is transmitted, or after the last bit of a synchronous frame has been transmitted. rir is activated when the received frame is moved to rbuf. note: while the receive task is handled by a single interrupt handler, the transmitter is serviced by two interrupt handlers. this provides advantages for the servicing software. for single transfers it is sufficient to use the transmitter interrupt (tir), which indicates that the previously loaded data has been transmitted, except for the last bit of an asynchronous frame. for multiple back-to-back transfers it is necessary to load the following piece of data at last until the time the last bit of the previous frame has been transmitted. in asynchronous mode this leaves just one bit-time for the handler to respond to the transmitter interrupt request, in synchronous mode it is impossible at all. using the transmit buffer interrupt (tbir) to reload transmit data gives the time to transmit a complete frame for the service routine, as tbuf may be reloaded while the previous data is still being transmitted. the start of autobaud operation interrupt abstir is generated whenever the autobaud detection unit is enabled (aben and abdeten and absten are set), and a start bit has been detected at rxd. in this case abstir is generated during autobaud detection whenever a start bit is detected. the autobaud detected interrupt abdetir is always generated after recognition of the second character of the two-byte frame, this means after a successful autobaud detection. if fcdeten is set the autobaud detected interrupt abdetir is also generated after the recognition of the first character of the two-byte frame.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-36 v2.2, 2004-01 asc_x, v2.0 figure 18-19 asc interrupt generation as shown in figure 18-19 , tbir is an early trigger for the reload routine, while tir indicates the completed transmission. therefore, software using handshake should rely on tir at the end of a data block to ensure that all data has actually been transmitted. the six interrupts of the asc0 and of the asc1 module are controlled by the following service request control registers: asc0_abic, asc1_abic: control the autobaud interrupts asc0_tic, asc1_tic: control the transmit interrupts asc0_ric, asc1_ric: control the receive interrupts asc0_eic, asc1_eic: control the error interrupts asc0_tbic, asc1_tbic: control the transmit buffer empty interrupt note: please refer to the general interrupt control register description for an explanation of the control fields. mct05450 start idle stop start stop start stop idle tbir tbir tir rir tbir tir rir tir rir asynchronous mode idle idle tbir tbir tir rir tbir tir rir tir rir synchronous mode asynchronous modes autobaud detection start idle stop abstir 1. character start abdetir 2. character stop abdetir 1) 1) only if fcdeten = 1
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-37 v2.2, 2004-01 asc_x, v2.0 the two autobaud interrupt request lines (start of autobaud detection and end of autobaud detection) in each asc module are ? ored ? together; the ? ored ? output signal is connected to the interrupt control register. this is shown in figure 18-20 . figure 18-20 wiring of autobaud interrupts table 18-12 summarizes all interrupt sources: table 18-12 asc interrupt sources interrupt signal description tbuf action tbir a write action to the transmit shift register from the transmit buffer register ascx_tbuf. if a fifo is configured for the asc and bit txtmen is cleared, txfifl defines when the interrupt is generated depending on the fifo fill state. transmit interrupt tir the interrupt is generated after the last (eight) data bit of a transmission frame is send via line txd by the transmit shift register. note: only for synchronous mode transmit interrupt tir the interrupt is generated just before the last bit of a transmission frame is send via line txd by the transmit shift register. if a fifo is configured for the asc and bit xtmen is cleared, txfifl defines when the interrupt is generated depending on the fifo fill state. note: only for asynchronous modes receive interrupt rir the interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register. note: only for synchronous mode mca05451 >1 _ start_autobaud_detect_irq end_autobaud_detect_irq ascx kernel ascx_abic (x = 0 ? 1)
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-38 v2.2, 2004-01 asc_x, v2.0 receive interrupt rir the interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register. if a fifo is configured for the asc and bit rxtmen is cleared, rxfifl defines when the interrupt is generated depending on the fifo fill state. note: only for asynchronous modes receive error interrupt rir and eir the interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register and the receive buffer contains already valid data. note: only for synchronous mode receive overflow rir and eir if an additional frame is received when the fifo is completely full an overflow error occurs. both interrupts are generated and the previously received frame is overwritten in the fifo and therefore lost. read to empty fifo eir a read operation from the cpu to an empty receive fifo generates this interrupt. transparent read operation rir in transparent mode a receive interrupt is always generated on a read operation from the cpu to the receive fifo if the fifo is not empty after this operation. flush action tbir a transmit buffer interrupt is generated when the transmit fifo is flushed. fifo enable tbir a transmit buffer interrupt is generated when the transmit fifo is enabled by setting bits txtmen and txfen when it was previously disabled in transparent mode. transmit overflow eir if an additional frame is written to the transmit fifo when it is completely full an overflow error occurred. the interrupt is generated and the previously written frame is overwritten and therefor lost in the fifo. frame error rir and eir an expected stop bit is not high. note: asynchronous mode only parity error rir and eir when a parity bit is received that does not fit to the parity of the received data. note: asynchronous mode only table 18-12 asc interrupt sources (cont ? d) interrupt signal description
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-39 v2.2, 2004-01 asc_x, v2.0 18.8 registers table 18-13 shows all registers which are required for programming the asc modules. it summarizes the asc kernel registers and the interrupt control registers and lists their addresses. table 18-13 asc module register summary name description asc0 addresses reg. area asc1 addresses 16-bit 8-bit 16-bit 8-bit ascx_con control register ffb0 h d8 h sfr ffb8 h dc h ascx_tbuf transmit buffer register feb0 h 58 h sfr feb8 h 5c h ascx_rbuf receive buffer register feb2 h 59 h sfr feba h 5d h ascx_abcon autobaud control register f1b8 h dc h esfr f1bc h de h ascx_abstat autobaud status register f0b8 h 5c h esfr f0bc h 5e h ascx_bg baudrate timer reload register feb4 h 5a h sfr febc h 5e h ascx_fdv fractional divider register feb6 h 5b h sfr febe h 5f h ascx_pmw irda pulse mode and width register feaa h 55 h sfr feac h 56 h ascx_rxfcon receive fifo control register f0c6 h 63 h esfr f0a6 h 53 h ascx_txfcon transmit fifo control register f0c4 h 62 h esfr f0a4 h 52 h ascx_fstat fifo status register f0ba h 5d h esfr f0be h 5f h ascx_abic autobaud interrupt control register f15c h ae h esfr f1ba h dd h ascx_tic transmit interrupt control register ff6c h b6 h sfr/ esfr f182 h c1 h ascx_ric receive interrupt control register ff6e h b7 h sfr/ esfr f18a h c5 h ascx_eic error interrupt control register ff70 h b8 h sfr/ esfr f192 h c9 h ascx_tbic transmit buffer interrupt control register f19c h ce h esfr f150 h a8 h
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-40 v2.2, 2004-01 asc_x, v2.0 control register the operating mode of the serial channel asc is controlled by its control register con. this register contains control bits for mode and error check selection, and status flags for error identification. ascx_con control register sfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 r lb brs odd fde oe fe pe oen fen pen/ rxdi ren stp m rw rw rw rw rw rwh rwh rwh rw rw rw rwh rw rw field bits type description r 15 rw baudrate generator run control bit 0 baudrate generator disabled (asc inactive) 1 baudrate generator enabled note: br_value should only be written if r = 0. lb 14 rw loopback mode enabled 0 loopback mode disabled. standard transmit/receive mode 1 loopback mode enabled brs 13 rw baudrate selection 0 baud rate timer prescaler divide-by-2 selected 1 baud rate timer prescaler divide-by-3 selected note: brs is don ? t care if fde = 1 (fractional divider selected). odd 12 rw parity selection 0 even parity selected (parity bit of 1 is included in data stream on odd number of 1 and parity bit of 0 is included in data stream on even number of 1) 1 odd parity selected (parity bit of 1 is included in data stream on even number of 1 and parity bit of 0 is included in data stream on odd number of 1)
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-41 v2.2, 2004-01 asc_x, v2.0 fde 11 rw fractional divider enable 0 fractional divider disabled 1 fractional divider enabled and used as prescaler for baudrate generator (bit brs is don ? t care) oe 10 rwh overrun error flag set by hardware on an overrun/underflow error (oen = 1). must be cleared by software. fe 9rwh framing error flag set by hardware on a framing error (fen = 1). must be cleared by software. pe 8rwh parity error flag set by hardware on a parity error (pen = 1). must be cleared by software. oen 7rw overrun check enable 0 ignore overrun errors 1 check overrun errors fen 6rw framing check enable (asynchronous mode only) 0 ignore framing errors 1 check framing errors pen / rxdi 5rw parity check enable/rxdi invert in irda mode all asynchronous modes without irda mode (pen): 0 ignore parity 1 check parity only in irda mode (rxdi): 0 rxd input is not inverted 1 rxd input is inverted ren 4rwh receiver enable bit 0 receiver disabled 1 receiver enabled note: ren is cleared by hardware after reception of a byte in synchronous mode. stp 3rw number of stop bits selection 0 one stop bit 1 two stop bits field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-42 v2.2, 2004-01 asc_x, v2.0 baudrate register the asc baudrate timer reload register bg contains the 13-bit reload value for the baudrate timer in asynchronous and synchronous mode. m [2:0] rw mode control 000 8-bit-data for synchronous operation 001 8-bit-data for asynchronous operation 010 8-bit-data irda mode for asynchronous operation 011 7-bit-data and parity for asynchronous operation 100 9-bit-data for asynchronous operation 101 8-bit-data and wake up bit for asynchronous operation 110 reserved. do not use this combination 111 8-bit-data and parity for asynchronous operation ascx_bg baudrate timer/reload reg. sfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 -br_value -rw field bits type description br_value [12:0] rw baudrate timer/reload value reading returns the 13-bit content of the baudrate timer; writing loads the baudrate timer/reload value. note: bg should only be written if r = 0. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-43 v2.2, 2004-01 asc_x, v2.0 fractional divider register the asc fractional divider register fdv contains the 9-bit divider value for the fractional divider (asynchronous mode only). it is also used for reference clock generation of the autobaud detection unit. ascx_fdv fractional divider register sfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 -fd_value -rw field bits type description fd_value [8:0] rw fractional divider register value fd_value contains the 9-bit value of the fractional divider which defines the fractional divider ratio n/512 (n = 0 ? 511). with n = 0, the fractional divider is switched off (input = output frequency, f div = f asc , see figure 18-14 ).
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-44 v2.2, 2004-01 asc_x, v2.0 irda pulse mode/width register the asc irda pulse mode and width register pmw contains the 8-bit irda pulse width value and the irda pulse width mode select bit. this register is only required in the irda operating mode. ascx_pmw irda pulse mode/width reg. sfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 - irp w pw_value -rw rw field bits type description irpw 8rw irda pulse width selection 0 irda pulse width is 3/16 bit time 1 irda pulse width is defined by pw_value pw_value [7:0] rw irda pulse width value pw_value is the 8-bit value n, which defines the variable pulse width of an irda pulse. depending on the asc input frequency f asc , this value can be used to adjust the irda pulse width to value which is not equal 3/16 bit time (e.g. 1.6 ms).
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-45 v2.2, 2004-01 asc_x, v2.0 transmitter buffer register the asc transmitter buffer register tbuf contains the transmit data value in asynchronous and synchronous mode. ascx_tbuf transmit buffer register sfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 -td_value -rw field bits type description td_value [8:0] rw transmit data register value tbuf contains the data to be transmitted in asynchronous and synchronous operating mode of the asc. data transmission is double buffered. therefore, a new value can be written to tbuf before the transmission of the previous value is complete.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-46 v2.2, 2004-01 asc_x, v2.0 receiver buffer register the asc receiver buffer register rbuf contains the transmit data value in asynchronous and synchronous modes. ascx_rbuf receive buffer register sfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 -rd_value -rw field bits type description rd_value [8:0] rw receive data register value rbuf contains the received data bits and, depending on the selected mode, the parity bit in asynchronous and synchronous operating mode of the asc. in asynchronous operating mode with m = 011 (7-bit data + parity) the received parity bit is written into rd7. in asynchronous operating mode with m = 111 (8-bit data + parity) the received parity bit is written into rd8.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-47 v2.2, 2004-01 asc_x, v2.0 autobaud control register the autobaud control register abcon of the asc module is used to control the autobaud detection operation. it contains its general enable bit, the interrupt enable control bits, and data path control bits. ascx_abcon autobaud control register esfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 - rx inv tx inv abem - fc det en ab det en abs t en aur en ab en - rw rw rw - rw rw rw rw rwh field bits type description rxinv 11 rw receive inverter enable 0 receive inverter disabled 1 receive inverter enabled txinv 10 rw transmit inverter enable 0 transmit inverter disabled 1 transmit inverter enabled abem [9:8] rw autobaud echo mode enable in echo mode the serial data at rxd is switched to txd output. 00 echo mode disabled 01 echo mode is enabled during autobaud detection 10 echo mode is always enabled 11 reserved; do not use this combination fcdeten 4rw first character of two-byte frame detected enable 0 autobaud detection interrupt abdetir becomes active after the two-byte frame recognition 1 autobaud detection interrupt abdetir becomes active after detection of the first and second byte of the two-byte frame abdeten 3rw autobaud detection interrupt enable 0 autobaud detection interrupt disabled 1 autobaud detection interrupt enabled
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-48 v2.2, 2004-01 asc_x, v2.0 absten 2rw start of autobaud detection interrupt enable 0 start of autobaud detection interrupt disabled 1 start of autobaud detection interrupt enabled auren 1rw automatic autobaud control of con.ren 0 con.ren is not affected during autobaud detection 1 con.ren is cleared (receiver disabled) when aben and auren are set together. con.ren is set (receiver enabled) after a successful autobaud detection (with the stop bit detection of the second character) aben 0rwh autobaud detection enable 0 autobaud detection is disabled 1 autobaud detection is enabled note: aben is reset by hardware after a successful autobaud detection; (with the stop bit detection of the second character). resetting aben by software if it was set aborts the autobaud detection. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-49 v2.2, 2004-01 asc_x, v2.0 autobaud status register the autobaud status register abstat of the asc module indicates the status of the autobaud detection operation. ascx_abstat autobaud status register esfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 - det wa it scc det scs det fcc det fcs det - rwh rwh rwh rwh rwh field bits type description detwait 4rwh autobaud detection is waiting 0 either character ? a ? , ? a ? , ? t ? , or ? t ? has been detected 1 the autobaud detection unit waits for the first ? a ? or ? a ? bit is cleared when either fcsdet or fccdet is set ( ? a ? or ? a ? detected). bit can be also cleared by software. detwait is set by hardware when aben is set. sccdet 3rwh second character with capital letter detected 0no capital ? t ? character detected 1 capital ? t ? character detected bit is cleared by hardware when aben is set or if fcsdet or fccdet or scsdet is set. bit can be also cleared by software. scsdet 2rwh second character with small letter detected 0no small ? t ? character detected 1small ? t ? character detected bit is cleared by hardware when aben is set or if fcsdet or fccdet or sccdet is set. bit can be also cleared by software.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-50 v2.2, 2004-01 asc_x, v2.0 note: scsdet or sccdet are set when the second character has been recognized. aben is reset and abdetir set after scsdet or sccdet have been set. fccdet 1rwh first character with capital letter detected 0no capital ? a ? character detected 1 capital ? a ? character detected bit is cleared by hardware when aben is set or if fcsdet or scsdet or sccdet is set. bit can be also cleared by software. fcsdet 0rwh first character with small letter detected 0no small ? a ? character detected 1small ? a ? character detected bit is cleared by hardware when aben is set or if fccdet or scsdet or sccdet is set. bit can be also cleared by software. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-51 v2.2, 2004-01 asc_x, v2.0 receive fifo control register ascx_rxfcon receive fifo control reg. esfr ( table 18-13 ) reset value: 0100 h 1514131211109876543210 -rxfitl - rx tm en rxf flu rxf en - rw - rw rw rw field bits type description rxfitl [11:8] rw receive fifo interrupt trigger level defines a receive fifo interrupt trigger level. a receive interrupt request (rir) is generated after the reception of a byte when the filling level of the receive fifo is equal to or greater than rxfitl. 0000 reserved. do not use this combination 0001 interrupt trigger level is set to one 0010 interrupt trigger level is set to two ?? 0111 interrupt trigger level is set to seven 1000 interrupt trigger level is set to eight note: in transparent mode this bitfield is don ? t care. note: combinations defining an interrupt trigger level greater than the fifo size should not be used. rxtmen 2rw receive fifo transparent mode enable 0 receive fifo transparent mode is disabled 1 receive fifo transparent mode is enabled note: this bit is don ? t care if the receive fifo is disabled (rxfen = 0).
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-52 v2.2, 2004-01 asc_x, v2.0 note: after a successful autobaud detection sequence, the rxfifo should be flushed before data is received. rxfflu 1rw receive fifo flush 0 no operation 1 receive fifo is flushed note: setting rxfflu clears bitfield rxffl in register fstat. rxfflu is always read as 0. rxfen 0rw receive fifo enable 0 receive fifo is disabled 1 receive fifo is enabled note: resetting rxfen automatically flushes the receive fifo. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-53 v2.2, 2004-01 asc_x, v2.0 transmit fifo control register ascx_txfcon transmit fifo control reg. esfr ( table 18-13 ) reset value: 0100 h 1514131211109876543210 -txfitl - tx tm en txf flu txf en - rw - rw rw rw field bits type description txfitl [11:8] rw transmit fifo interrupt trigger level defines a transmit fifo interrupt trigger level. a transmit interrupt request (tir) is generated after the transfer of a byte when the filling level of the transmit fifo is equal to or lower than txfitl. 0000 reserved. do not use this combination 0001 interrupt trigger level is set to one 0010 interrupt trigger level is set to two ?? 0111 interrupt trigger level is set to seven 1000 interrupt trigger level is set to eight note: in transparent mode this bitfield is don ? t care. note: combinations defining an interrupt trigger level greater than the fifo size should not be used. txtmen 2rw transmit fifo transparent mode enable 0 transmit fifo transparent mode is disabled 1 transmit fifo transparent mode is enabled note: this bit is don ? t care if the receive fifo is disabled (txfen = 0).
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-54 v2.2, 2004-01 asc_x, v2.0 txfflu 1rw transmit fifo flush 0 no operation 1 transmit fifo is flushed note: setting txfflu clears bitfield txffl in register ascx_fstat. txfflu is always read as 0. txfen 0rw transmit fifo enable 0 transmit fifo is disabled 1 transmit fifo is enabled note: resetting txfen automatically flushes the transmit fifo. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-55 v2.2, 2004-01 asc_x, v2.0 fifo status register ascx_fstat fifo status register esfr ( table 18-13 ) reset value: 0000 h 1514131211109876543210 - txffl - rxffl -rh-rh field bits type description txffl [11:8] rh transmit fifo filling level 0000 transmit fifo is filled with zero bytes 0001 transmit fifo is filled with one byte ?? 0111 transmit fifo is filled with seven bytes 1000 transmit fifo is filled with eight bytes note: txffl is cleared after a receive fifo flush operation. rxffl [3:0] rh receive fifo filling level 0000 receive fifo is filled with zero bytes 0001 receive fifo is filled with one byte ?? 0111 receive fifo is filled with seven bytes 1000 receive fifo is filled with eight bytes note: rxffl is cleared after a receive fifo flush operation.
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-56 v2.2, 2004-01 asc_x, v2.0 18.9 interfaces of the asc modules in the XC161 the asc modules are connected to io ports and other internal modules according to figure 18-21 and figure 18-22 . the input/output lines of asc0 and asc1 are connected to pins of ports p3. the 6 interrupt request lines of each module are connected to the interrupt control block. clock control and emulation control of the ssc module is handled by the system control unit, scu. figure 18-21 asc0 module interfaces figure 18-22 asc1 module interfaces interrupt control block asc0 module mca05452 port p3 control system control unit (scu) p3.11/rxda0 p3.10/txda0 s0tirq s0abirq2 s0rirq s0eirq s0tbirq s0abirq1 asc0dis f asc s0rxd s0txd interrupt control block asc1 module mca05453 port p3 control system control unit (scu) p3.1/rxda1 p3.0/txda1 s1tirq s1abirq2 s1rirq s1eirq s1tbirq s1abirq1 asc1dis f asc s1rxd s1txd
XC161 derivatives peripheral units (vol. 2 of 2) asynchronous/synchronous serial interface (asc) user ? s manual 18-57 v2.2, 2004-01 asc_x, v2.0 note: in synchronous operating mode, the direction of the rxd pin is not automatically set by the asc modules; it must be switched by software via the corresponding bit in register dp3, depending on the selected mode (receive or transmit data). note: to select rxda1 as alternate output function for p3.1, it is sufficient to set bit 1 of register altsel0p3, the corresponding bit in register altsel1p3 is ? don ? t care ? .
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-1 v2.2, 2004-01 ssc_x, v2.0 19 high-speed synchronous serial interface (ssc) the XC161 contains two high-speed synchronous serial interfaces, ssc0 and ssc1. the following sections present the general features and operations of such an ssc module. the final section describes the actual implementation of the two ssc modules including their interconnections with other on-chip modules. 19.1 introduction the high-speed synchronous serial interface (ssc) supports both full-duplex and half- duplex serial synchronous communication up to 20 mbit/s (@ 40 mhz module clock). the serial clock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift direction, clock polarity, and phase are programmable. this supports communication with spi-compatible devices. transmission and reception of data is double-buffered. a 16-bit baudrate generator provides the ssc with a separate serial clock signal. features and functions master and slave mode operation ? full-duplex or half-duplex operation flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift direction: lsb or msb shift first ? programmable clock polarity: idle low or high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock baudrate generation from 20 mbit/s to 306.6 bit/s (@ 40 mhz module clock) interrupt generation ? on a transmitter-empty condition ? on a receiver-full condition ? on an error condition (receive, phase, baudrate, transmit error) 19.2 operational overview the high-speed synchronous serial interface can be configured in a very flexible way, so it can be used with other synchronous serial interfaces, can serve for master/slave or multimaster interconnections or can operate compatible with the popular spi interface. thus, the ssc can be used to communicate with shift registers (io expansion), peripherals (e.g. eeproms, etc.) or other controllers (networking). the ssc supports half-duplex and full-duplex communication. data is transmitted on lines mtx/stx or received on lines mrx/srx, connected with pins mtsr (master transmit/slave receive) and mrst (master receive/slave transmit). the clock signal is output via line
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-2 v2.2, 2004-01 ssc_x, v2.0 msclk (master serial shift clock) or input via line ssclk (slave serial shift clock). both lines are connected to pin sclk. these pins are alternate functions of port pins. a block diagram of the ssc module is shown in figure 19-2 . from the programmer ? s point of view, the term ? ssc unit ? refers to a set of registers (see figure 19-1 ) which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and including their direction control bits. figure 19-1 sfrs associated with the ssc unit mca05454 p1h dp1h altsel0p1h syscon3 opsen p3 dp3 altsel0p3 ssc0 ssc1 tic ric eic con br tb rb system registers interrupt registers control registers data registers transmit / receive buffer register ssc control register baudrate timer / reload register transmit / receive / error interrupt control register port py data register (y = 1h, 3) port py direction control register (y = 1h, 3) port py alternate output select register 0 (y = 1h, 3) scu system control register 3 tb / rb con br tic / ric / eic py dpy altsel0py syscon3
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-3 v2.2, 2004-01 ssc_x, v2.0 figure 19-2 synchronous serial channel (ssc) block diagram 19.2.1 operating mode selection the operating mode of the ssc module is controlled by its control register sscx_con. this register has a double function: during programming (ssc disabled by sscx_con.en = 0), it provides access to a set of control bits during operation (ssc enabled by sscx_con.en = 1), it provides access to a set of status flags in the following, the layout of register con is shown for both functions. mcb05455 baudrate generator clock control ssc control block tirq rirq eirq transmit interrupt receive interrupt request error interrupt request status control 16-bit shift register 16-bit shift register 16-bit shift register input/ output line control mtx mrx stx srx f ssc to pin sclk to pin mtsr to pin mrst msclk ssclk
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-4 v2.2, 2004-01 ssc_x, v2.0 ssc control register (sscx_con.en = 0: programming mode) sscx_con ssc control register sfr ( table 19-2 ) reset value: 0000 h 1514131211109876543210 en = 0 ms - a ren ben pen ren ten lb po ph hb bm rwrw - rwrwrwrwrwrwrwrwrw rw field bits type description en 15 rw enable bit = 0 transmission and reception disabled. access to control bits. ms 14 rw master select 0 slave mode. operate on shift clock received via sclk. 1 master mode. generate shift clock and output it via sclk. aren 12 rw automatic reset enable 0 no additional action upon a baudrate error 1 the ssc is automatically reset upon a baudrate error ben 11 rw baudrate error enable 0 ignore baudrate errors 1 check baudrate errors pen 10 rw phase error enable 0 ignore phase errors 1 check phase errors ren 9rw receive error enable 0 ignore receive errors 1 check receive errors ten 8rw transmit error enable 0 ignore transmit errors 1 check transmit errors lb 7rw loop back control 0 normal output 1 receive input is connected with transmit output (half-duplex mode)
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-5 v2.2, 2004-01 ssc_x, v2.0 ssc control register (sscx_con.en = 1: operating mode) po 6rw clock polarity control 0 idle clock line is low, leading clock edge is low- to-high transition. 1 idle clock line is high, leading clock edge is high-to-low transition. ph 5rw clock phase control 0 shift transmit data on the leading clock edge, latch on trailing edge. 1 latch receive data on leading clock edge, shift on trailing edge. hb 4rw heading control 0 transmit/receive lsb first 1 transmit/receive msb first bm [3:0] rw data width selection 0000 reserved. do not use this combination. 0001 transfer data width is 2 bits ? transfer data width is ( + 1) 1111 transfer data width is 16 bits sscx_con ssc control register sfr ( table 19-2 ) reset value: 0000 h 1514131211109876543210 en = 1 ms-bsybeperete---- bc rw rw - rh rwh rwh rwh rwh---- rw field bits type description en 15 rw enable bit = 1 transmission and reception enabled. access to status flags and m/s control. ms 14 rw master/slave selection 0 slave mode. operate on shift clock received via sclk. 1 master mode. generate shift clock and output it via sclk. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-6 v2.2, 2004-01 ssc_x, v2.0 note: the target of an access to sscx_con (control bits or flags) is determined by the state of bit en prior to the access; that is, writing c057 h to sscx_con in programming mode (en = 0) will initialize the ssc (en was 0) and then turn it on (en = 1). when writing to sscx_con, ensure that reserved locations receive zeros. transmitter buffer register the ssc transmit buffer register sscx_tb (see table 19-2 ) contains the transmit data value. unselected bits of sscx_tb are ignored during transmission. the transmit value must be right-aligned regardless of msb or lsb first operation. receiver buffer register the ssc receive buffer register sscx_rb (see table 19-2 ) contains the receive data value. unselected bits of sscx_rb will be not valid and should be ignored. the received value is always right-aligned regardless of msb or lsb first operation. bsy 12 rh busy flag set while a transfer is in progress. do not write to!!! be 11 rwh baudrate error flag 0 no error 1 more than factor 2 or 0.5 between slave ? s actual and expected baudrate pe 19 rwh phase error flag 0 no error 1 the received data has changed around sampling clock edge re 9rwh receive error flag 0 no error 1 a reception was completed before the receive buffer was read te 8rwh transmit error flag 0 no error 1 a transfer has started with the slave ? s transmit buffer not being updated bc [3:0] rh bit count field shift counter is updated with every shifted bit. do not write to!!! field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-7 v2.2, 2004-01 ssc_x, v2.0 the shift register of the ssc is connected to both, the transmit lines and the receive lines via the pin control logic (see block diagram in figure 19-2 ). transmission and reception of serial data are synchronized and take place at the same time, i.e. the same number of transmitted bits is also received. to prepare for a transfer, the transmit data is written into the transmit buffer (sscx_tb) by software. it is moved to the shift register as soon as this is empty. an ssc master (con.ms = 1) immediately begins transmitting, while an ssc slave (con.ms = 0) will wait for an active shift clock. when the transfer starts, the busy flag con.bsy is set and the transmit interrupt request line tirq will be activated to indicate that register sscx_tb may be reloaded again. when the programmed number of bits (2 ? 16) has been transferred, the contents of the shift register are moved to the receive buffer sscx_rb and the receive interrupt request line rirq is activated. if no further transfer is to take place (sscx_tb is empty), con.bsy will be cleared at the same time. software should not modify con.bsy, as this flag is hardware controlled. note: only one ssc can be master at a given time in a serial system. the transfer of serial data bits can be programmed in many respects: the data width can be specified from 2 bits to 16 bits a transfer may start with either the lsb or the msb the shift clock may be idle low or idle high the data bits may be shifted with the leading edge or the trailing edge of the shift clock signal the baudrate may be set from 306.6 bit/s up to 20 mbit/s (@ 40 mhz module clock) the shift clock can be generated (msclk) or can be received (ssclk) these features allow the adaptation of the ssc to a wide range of applications in which serial data transfer is required. the data width selection supports the transfer of frames of any data length, from 2-bit ? characters ? up to 16-bit ? characters ? . starting with the lsb (con.hb = 0) enables communication with ssc devices in synchronous mode or with 8051-like serial interfaces, for example. starting with the msb (con.hb = 1) enables operation compatible with the spi interface. regardless of the data width selected and whether the msb or the lsb is transmitted first, the transfer data is always right-aligned in registers sscx_tb and sscx_rb, with the lsb of the transfer data in bit 0 of these registers. the data bits are rearranged for transfer by the internal shift register logic. the unselected bits of sscx_tb are ignored; the unselected bits of sscx_rb will not be valid and should be ignored by the receiver service routine. the clock control allows the adaptation of transmit and receive behavior of the ssc to a variety of serial interfaces. a specific shift clock edge (rising or falling) is used to shift out transmit data, while the other shift clock edge is used to latch in receive data. bit ph selects the leading edge or the trailing edge for each function. bit po selects the level of
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-8 v2.2, 2004-01 ssc_x, v2.0 the shift clock line in the idle state. thus, for an idle-high clock, the leading edge is a falling edge, a 1-to-0 transition (see figure 19-3 ). figure 19-3 serial clock phase and polarity options 19.2.2 full-duplex operation in a full-duplex serial configuration, illustrated in figure 19-4 , the various devices are connected via three lines. the definition of these lines is always determined by the master: the line connected to the master ? s data output line mtsr is the transmit line; the receive line is connected to its data input line mrst; the shift clock line is sclk. only the device selected for master operation generates and outputs the shift clock on line sclk. all slaves receive this clock; thus, their sclk pin must be switched to input mode. the output of the master ? s shift register is connected to the external transmit line, which in turn is connected to the slaves ? shift register inputs. the outputs of the slaves ? shift register are connected to the external receive line in order to enable the master to receive the data shifted out of the slaves. the external connections are hard-wired, the function and direction of these pins is determined by the master or slave operation of the individual device. note: the shift direction shown in figure 19-4 applies for msb-first operation as well as for lsb-first operation. when initializing the devices in this configuration, one device must be selected for master operation while all other devices must be programmed for slave operation. initialization includes the operating mode of the device ? s ssc and also the function of the respective port lines. con. po con. ph 0 0 0 1 1 0 1 1 mct05456 shift clock sclk pins mtsr/mrst first bit latch data shift data transmit data last bit
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-9 v2.2, 2004-01 ssc_x, v2.0 figure 19-4 ssc full-duplex configuration the data output pins mrst of all slave devices are connected together onto the one receive line in the configuration shown in figure 19-4 . during a transfer, each slave shifts out data from its shift register. there are two ways to avoid collisions on the receive line due to different slave data: only one slave drives the line, i.e. enables the driver of its mrst pin. all the other slaves must have their mrst pins programmed as input so only one slave can put its data onto the master ? s receive line. only receiving data from the master is possible. the master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. the selected slave then switches its mrst line to output until it gets a de-selection signal or command. in the configuration depicted in figure 19-4 , device #2 is the slave which has its output driver enabled as push/pull output. device #3 is an inactive slave, it needs to disable its output driver by programming the pin to input mode. the slaves use their mrst outputs in open-drain mode. this forms a wired-and connection. the receive line needs an external pull-up in this case. corruption of the clock mca05457 master device #1 transmit receive clock mtsr sclk mrst shift register clock mtsr sclk mrst shift register clock device #2 slave mtsr sclk mrst shift register device #3 slave symbols input push/pull output open-drain output tri-stated = input
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-10 v2.2, 2004-01 ssc_x, v2.0 data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master only send ones (1). because this high level is not actively driven onto the line, but only held through the pull-up device, the selected slave can pull this line actively to a low level when transmitting a zero bit. the master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave. after performing the necessary initialization of the ssc, the serial interfaces can be enabled. for a master device, the clock line msclk will now go to its programmed polarity. the output data line mtx will go to either 0 or 1 until the first transfer will start. after a transfer, the data line mtx will always remain at the logic level of the last transmitted data bit. when the serial interfaces are enabled, the master device can initiate the first data transfer by writing the transmit data into register sscx_tb. this value is copied into the shift register (assumed to be empty at this time), and the selected first bit of the transmit data will be placed onto the transmit line mtsr on the next clock from the baudrate generator (transmission starts only if bit en = 1). depending on the selected clock phase, a clock pulse will also be generated on the sclk line. at the same time, with the opposite clock edge, the master latches and shifts in the data detected at its input line mrst. this ? exchanges ? the transmit data with the receive data. because the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master ? s shift register, shifting out the data contained in the registers, and shifting in the data detected at the input line. after the preprogrammed number of clock pulses (via the data width selection), the data transmitted by the master is contained in all the slaves ? shift registers, while the master ? s shift register holds the data of the selected slave. in the master and all slaves, the contents of the shift register are copied into the receive buffer sscx_rb and the receive interrupt line rirq is activated. a slave device will immediately output the selected first bit (msb or lsb of the transfer data) at line mrst when the contents of the transmit buffer are copied into the slave ? s shift register. bit bsy is not set until the first clock edge at sclk appears. the slave device will not wait for the next clock from the baudrate generator, as the master does. the reason for this is that, depending on the selected clock phase, the first clock edge generated by the master may already be used to clock in the first data bit. thus, the slave's first data bit must already be valid at this time. note: on the ssc, a transmission and a reception takes place at the same time, regardless of whether valid data has been transmitted or received. note: the initialization of the clk pin on the master requires some attention in order to avoid undesired clock transitions, which may disturb the other devices. before the clock pin is switched to output via the related direction control register, the clock output level shall be selected in the control register sscx_con and the alternate output be prepared via the related altsel register, or the output latch must be loaded with the clock idle level.
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-11 v2.2, 2004-01 ssc_x, v2.0 19.2.3 half-duplex operation in a half-duplex configuration, only one data line is necessary for both, receiving and transmitting of data. the data exchange line is connected to both, the mtsr and mrst pins of each device, the shift clock line is connected to the sclk pin. the master device controls the data transfer by generating the shift clock, while the slave devices receive it. due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. similar to full-duplex mode, there are two ways to avoid collisions on the data exchange line: only the transmitting device may enable its transmit pin driver the non-transmitting devices use open-drain outputs and send only ones (1s). because the data inputs and outputs are connected together, a transmitting device will clock in its own data at the input pin (mrst for a master device, mtsr for a slave). by this method, any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data. figure 19-5 ssc half-duplex configuration clock mca05458 master device #1 transmit clock mtsr sclk mrst shift register clock mtsr sclk mrst shift register clock device #2 slave mtsr sclk shift register device #3 slave symbols input push/pull output open-drain output tri-stated = input mrst
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-12 v2.2, 2004-01 ssc_x, v2.0 19.2.4 continuous transfers when the transmit interrupt request flag is set, it indicates that the transmit buffer sscx_tb is empty and ready to be loaded with the next transmit data. if sscx_tb has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay. on the data line, there is no gap between the two successive frames. for example, two 8-bit transfers would look the same as one 16-bit transfer. this feature can be used to interface with devices that can operate with or require more than 16 data bits per transfer. it is just a matter of software, how long a total data frame length can be. this option can also be used to interface to byte-wide and word-wide devices on the same serial bus, for instance. note: of course, this can happen only in multiples of the selected basic data width, because it would require disabling/enabling of the ssc to reprogram the basic data width on-the-fly. 19.2.5 baudrate generation the serial channel ssc has its own dedicated 16-bit baudrate generator with 16-bit reload capability, facilitating baudrate generation independent of the timers. figure 19-6 shows the baudrate generator of the ssc in more detail. figure 19-6 ssc baudrate generator the baudrate generator is clocked with the module clock f ssc . the counter counts downwards. access to the baudrate generator is performed via one register, sscx_br, described below. mca05459 16-bit reload register 16-bit counter f sclk 2 f ssc f sclkmax in master mode f sclkmax in slave mode f ssc / 2 f ssc / 4
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-13 v2.2, 2004-01 ssc_x, v2.0 baudrate timer/reload register the ssc baudrate timer/reload register sscx_br has a double function. while the ssc is disabled, it serves as the reload register for the baudrate timer. writing to it loads the timer reload register with the written reload value. reading returns the current reload value. while the ssc is enabled, this register reflects the current baudrate timer contents. writing to this register is not allowed while the ssc is enabled. baudrate calculation the timer is loaded with the reload value and starts counting immediately when the ssc is enabled. the formulas below calculate either the resulting baudrate for a given reload value, or the required reload value for a given baudrate: (19.1)
represents the contents of the reload register, taken as unsigned 16-bit integer; while baudrate is equal to f sclk as shown in figure 19-6 . the maximum baudrate that can be achieved when using a module clock of 40 mhz is 20 mbit/s in master mode (with
= 0000 h ) or 10 mbit/s in slave mode (with
= 0001 h ). table 19-1 lists some possible baudrates together with the required reload values and the resulting bit times, assuming a module clock of 40 mhz. table 19-1 typical baudrates of the ssc ( f ssc = 40 mhz) reload value baudrate (= f sclk )deviation 0000 h 20 mbit/s (only in master mode) 0.0% 0001 h 10 mbit/s 0.0% 0009 h 2 mbit/s 0.0% 0013 h 1 mbit/s 0.0% 001a h 750 kbit/s -1.25% 0027 h 500 kbit/s 0.0% 0063 h 200 kbit/s 0.0% 00c7 h 100 kbit/s 0.0% ffff h 306.6 bit/s 0.0% baudrate f ssc 2
1 + () --------------------------------------- = bg f ssc 2 baudrate ------------------------------------ 1 ? =
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-14 v2.2, 2004-01 ssc_x, v2.0 19.2.6 error detection mechanisms the ssc is able to detect four different error conditions. receive error and phase error are detected in all modes; transmit error and baudrate error only apply to slave mode. when an error is detected, the respective error flag in register sscx_con is set and an error interrupt request will be generated by activating the eirq line (see figure 19-7 ). the error interrupt handler may then check the error flags to determine the cause of the error interrupt. the error flags are not reset automatically but rather must be cleared by software after servicing. this allows servicing of some error conditions via interrupt, while the others may be polled by software. note: the error interrupt handler must clear the associated (enabled) error flag(s) to prevent repeated interrupt requests. figure 19-7 ssc error interrupt control a receive error (master or slave mode) is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register sscx_rb. this condition sets the error flag re and, when enabled via bit ren, the error interrupt request line eirq. the old data in the receive buffer sscx_rb will be overwritten with the new value and is irretrievably lost. a phase error (master or slave mode) is detected when the incoming data at pin mrst (master mode) or mtsr (slave mode), sampled with the same frequency as the module mca05460 & & & & bits in register con >1 _ error interrupt request eirq ten ren pen ben te re pe be error transmit error receive error phase error baudrate
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-15 v2.2, 2004-01 ssc_x, v2.0 clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal sclk. this condition sets the error flag pe and, when enabled via bit pen, the error interrupt request line eirq. a baudrate error (slave mode) is detected when the incoming clock signal deviates from the programmed baudrate by more than 100%, i.e. it either is more than double or less than half the expected baudrate. this condition sets the error flag be and, when enabled via bit ben, the error interrupt request line eirq. using this error detection capability requires that the slave ? s baudrate generator is programmed to the same baudrate as the master device. this feature detects false, additional or missing, pulses on the clock line (within a certain frame). note: if this error condition occurs and bit aren = 1, an automatic reset of the ssc will be performed in case of this error. this is done to re-initialize the ssc if too few or too many clock pulses have been detected. a transmit error (slave mode) is detected when a transfer was initiated by the master (sclk gets active), but the transmit buffer sscx_tb of the slave was not updated since the last transfer. this condition sets the error flag te and, when enabled via bit ten, the error interrupt request line eirq. if a transfer starts while the transmit buffer is not updated, the slave will shift out the ? old ? contents of the shift register, which usually is the data received during the last transfer. this may lead to corruption of the data on the transmit/receive line in half-duplex mode (open-drain configuration) if this slave is not selected for transmission. this mode requires that slaves not selected for transmission only shift out ones; that is, their transmit buffers must be loaded with ffff h prior to any transfer. note: a slave with push/pull output drivers not selected for transmission will usually have its output drivers switched off. however, in order to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer. the cause of an error interrupt request (receive, phase, baudrate, transmit error) can be identified by the error status flags in control register sscx_con. note: the error status flags te, re, pe, and be, are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software.
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-16 v2.2, 2004-01 ssc_x, v2.0 19.2.7 ssc register summary table 19-2 ssc module register summary name description ssc0 addresses reg. area ssc1 addresses 16-bit 8-bit 16-bit 8-bit sscx_con control register ffb2 h d9 h sfr ff5e h af h sscx_br baudrate timer reload register f0b4 h 5a h esfr f05e h 2f h sscx_tb transmit buffer register f0b0 h 58 h esfr f05a h 2d h sscx_rb receive buffer register f0b2 h 59 h esfr f05c h 2e h sscx_tic transmit interrupt control register ff72 h b9 h sfr/ esfr f1aa h d5 h sscx_ric receive interrupt control register ff74 h ba h sfr/ esfr f1ac h d6 h sscx_eic error interrupt control register ff76 h bb h sfr/ esfr f1ae h d7 h
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-17 v2.2, 2004-01 ssc_x, v2.0 19.2.8 port configuration requirements table 19-3 shows the required register setting to configure the io lines of the ssc modules for master or slave mode operation. note: the direction control bits in registers dp3 or dp1h must be set or cleared by software depending on the mode of operation selected (master or slave mode). they are not controlled automatically by the ssc modules. table 19-3 ssc0/ssc1 io selection and setup module mode port lines alternate select register direction and port output register io ssc0 master p3.8 / mrst0 altsel0p3.p8 = 1 dp3.p8 = 0 input p3.9 / mtsr0 altsel0p3.p9 = 1 dp3.p9 = 1 and p3.p9 = 1 output p3.13 / sclk0 altsel0p3.p13 = 1 dp3.p13 = 1 and p3.p13 = 1 output slave p3.8 / mrst0 altsel0p3.p8 = 1 dp3.p8 = 1 and p3.p8 = 1 output p3.9 / mtsr0 altsel0p3.p9 = 1 dp3.p9 = 0 input p3.13 / sclk0 altsel0p3.p13 = 1 dp3.p13 = 0 input ssc1 master p1h.1 / mrst1 altsel0p1h.p1 = 1 dp1h.p1 = 0 input p1h.2 / mtsr1 altsel0p1h.p2 = 1 dp1h.p2 = 1 output p1h.3 / sclk1 altsel0p1h.p3 = 1 dp1h.p3 = 1 output slave p1h.1 / mrst1 altsel0p1h.p1 = 1 dp1h.p1 = 1 output p1h.2 / mtsr1 altsel0p1h.p2 = 1 dp1h.p2 = 0 input p1h.3 / sclk1 altsel0p1h.p3 = 1 dp1h.p3 = 0 input
XC161 derivatives peripheral units (vol. 2 of 2) high-speed synchronous serial interface (ssc) user ? s manual 19-18 v2.2, 2004-01 ssc_x, v2.0 19.3 interfaces of the ssc modules in the XC161 the ssc modules are connected to io ports and other internal modules according to figure 19-8 and figure 19-9 . the input/output lines of ssc0 are connected to pins of ports p3, while the input/output lines of ssc1 are connected to pins of ports p1h. the three interrupt request lines of each module are connected to the interrupt control block. clock control and emulation control of the ssc module is handled by the system control unit, scu. figure 19-8 ssc0 module interfaces figure 19-9 ssc1 module interfaces ssc0 module mca05461 port p3 control system control unit (scu) ssc0dis f ssc interrupt control block ssc0_tirq ssc0_rirq ssc0_eirq p3.9/mtsr0 p3.8/mrst0 mtx mrx stx srx msclk ssclk p3.13/sclk0 ssc1 module mca05462 port p1h control system control unit (scu) ssc1dis f ssc interrupt control block ssc1_tirq ssc1_rirq ssc1_eirq p1h.2/mtsr1 p1h.1/mrst1 mtx mrx stx srx msclk ssclk p1h.3/sclk1
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-1 v2.2, 2004-01 iic_x, v2.0 20 iic-bus module the iic-bus supports a defined protocol to enable devices to communicate directly with each other via a simple two-wire serial interface. one line is responsible for clock transfer and synchronization (scl), the other is responsible for the data transfer (sda). the on-chip iic-bus module connects the XC161 to other external controllers and/or peripherals via the two-line serial iic-bus interface. the iic-bus module provides communication at data rates of up to 400 kbit/s and features 7-bit addressing as well as 10-bit addressing. this module is fully compatible to the iic bus protocol. the module can operate in three different modes: master mode , where the iic-bus module controls the bus transactions and provides the clock signal. slave mode , where an external master controls the bus transactions and provides the clock signal. multimaster mode , where several masters can be connected to the bus, i.e. the iic-bus module can be master or slave. the on-chip iic-bus module allows efficient communication via the common iic-bus. the module unloads the cpu of low level tasks like serialization/de-serialization of bus data generation of start and stop conditions monitoring of the bus lines evaluation of the device address in slave mode bus access arbitration in multi-master mode features extended buffer allows up to 4 transmit/receive data bytes to be stored selectable baudrate generation support of standard 100 kbit/s and extended 400 kbit/s data rates operation in 7-bit addressing or 10-bit addressing mode flexible control via interrupt service routines or by polling dynamic access to up to 3 physical iic buses applications eeproms 7-segment displays keyboard controllers on-screen display audio processors
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-2 v2.2, 2004-01 iic_x, v2.0 20.1 overview a block diagram of the XC161 iic-bus module is shown in figure 20-1 , while figure 20-2 illustrates a possible serial interface system. figure 20-1 iic-bus module block diagram the iic-bus module has its own flexible baudrate generator. a 4-byte receive/transmit buffer enables software to write or read longer message and eliminates the need to react after each received/transmitted byte. serialization and de-serialization of the byte data is performed via an 8-bit shift register. the address logic analyzes the received slave address and informs the control logic when the device has been contacted by another station in the system. the control and status logic controls the entire module and provides a number of status signals and flags, reflecting the conditions of the module to the software. to operate in an iic-bus system, it is not only necessary for a station to be able to drive the clock and data lines of the iic-bus, but also to monitor the actual levels on these lines and to detect special conditions, such as the start and stop conditions, and to perform clock synchronization as well as bus arbitration. this is handled by the iic-bus driver and monitor block. in addition, this block provides the port pin enable control for the three possible scl/sda signal pairs. due to the feature that the iic-bus module of the XC161 can control up to three scl/sda signal pairs, it is possible to build a system with separate iic-buses as shown in figure 20-2 . mcb05463 baudrate generator module control & status logic receive/ transmit buffer shift register address logic iic-bus driver & monitor dirq interrupt request pirq interrupt request clock line scl pin enable lines data line sda f iic
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-3 v2.2, 2004-01 iic_x, v2.0 note: per definition, an iic-bus system is a wired-and configuration. the active (dominant) level is the low level, while the high level is not actively driven by the stations (or nodes), but held through external pull-up devices. for this purpose, the respective pin drivers must be switched to open drain mode. figure 20-2 iic-bus configuration example in an iic-bus system, a station may be able to play different roles: master-transmitter (a master device which is sending data to one or more slaves), master-receiver (a master which is receiving data from a slave), slave-transmitter (a slave which is sending data to a master) and slave-receiver. mca05464 sda0 scl0 sda1 scl1 on-chip iic-bus module iic bus node #y iic bus node #x iic-bus a iic-bus b
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-4 v2.2, 2004-01 iic_x, v2.0 from the programmer ? s point of view, the term ? iic-bus module ? refers to a set of registers which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and including their direction control bits. figure 20-3 shows the special function registers (sfrs) associated with the iic-bus module. figure 20-3 sfrs associated with the iic-bus module p9 dp9 odp9 dic peic con cfg rtbl rtbh system registers interrupt registers control/status reg. data registers adr st altsel0p9 altsel1p9 syscon3 opsen mca05465 receive / transmit buffer register control register configuration register address register data interrupt control register protocol event interrupt control register port p9 data register port p9 direction control register port p9 open-drain control register port p9 alternate output select register (x = 0, 1) scu system control register 3 scu ocds peripheral suspend enable register rtbl / rtbh con cfg adr dic peic p9 dp9 odp9 altselxp9 scu_syscon3 scu_opsen
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-5 v2.2, 2004-01 iic_x, v2.0 20.2 register description in the following, the registers of the iic-bus module are described in detail. iic_con control register xsfr (e602 h /--) reset value: 0000 h 1514131211109876543210 ---- ci stpigetrxint ack dis bum mod rsc m10 ---- rw rwh rw rwh rw rwh rwh rw rwh rw field bits type description ci [11:10] rw transmit buffer length control 00 1 byte (rtb0) 01 2 bytes (rtb1 ? rtb0) 10 3 bytes (rtb2 ? rtb0) 11 4 bytes (rtb3 ? rtb0) stp 9rwh master stop control 0 no action 1 setting bit stp generates a stop condition after the next transmission. bit bum is cleared. note: stp is automatically cleared by a stop condition. ige 8rw ignore end-of-transmission (irqe) interrupt 0 the iic is stopped at irqe interrupt 1 the iic ignores the irqe interrupt trx 7rwh transmit select 0 no data is transmitted to the iic bus 1 data is transmitted to the iic bus note: trx is set automatically when writing to the transmit buffer. trx is automatically cleared after the last byte as a slave transmitter. int 6rw interrupt flag clear control 0 interrupt flag irqd is cleared by a read/write access to rtb0 ? 3 1 interrupt flag irqd is not cleared by a read/write access to rtb0 ? 3
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-6 v2.2, 2004-01 iic_x, v2.0 ackdis 5rwh acknowledge pulse disable 0 an acknowledge pulse is generated for each received byte 1 no acknowledge pulse is generated note: ackdis is automatically cleared by a stop condition. bum 4rwh busy master 0 clearing bit bum immediately generates a stop condition 1 setting bit bum generates a start condition in (multi-) master mode note: setting bit bum while the bus is busy (bb = 1) generates an arbitration lost situation. in this case, bum is cleared and bit al is set. bum cannot be set in slave mode. mod [3:2] rw basic operating mode 00 iic module is disabled and initialized (init- mode). transmissions in progress will be aborted. 01 slave mode 10 single-master mode 11 multi-master mode rsc 1rwh repeated start condition trigger 0 no operation 1 generate a repeated start condition in (multi-) master mode. rsc cannot be set in slave mode. note: rsc is cleared automatically after the repeated start condition has been sent. m10 0rw slave address width selection 0 7-bit slave address, using ica[7:1] 1 10-bit slave address, using ica[9:0] field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-7 v2.2, 2004-01 iic_x, v2.0 iic_st status register xsfr (e604 h /--) reset value: 0000 h 1514131211109876543210 ----- co irq e irq p irq d bb lrb sla al adr ----- rh rwh rwh rwh rh rh rh rwh rh field bits type description co [10:8] rh transmit byte counter displays the number of correctly transferred bytes. see section 20.3.4 for details. 000 0 bytes 001 1 byte 010 2 bytes 011 3 bytes 100 4 bytes 1xx reserved irqe 7rwh end-of-data-transmission interrupt req. flag 0 no interrupt request pending 1 an end-of-data-transmission interrupt request is pending see section 20.4 for details. irqp 6rwh protocol event interrupt request flag 0 no interrupt request pending 1 a protocol event interrupt request is pending see section 20.4 for details. irqd 5rwh data transfer event interrupt request flag 0 no interrupt request pending 1 a data transfer event interrupt request is pending see section 20.4 for details. bb 4rh bus busy flag 0 the iic-bus is idle 1 the iic-bus is busy note: bit bb is always 0 while the iic module is disabled.
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-8 v2.2, 2004-01 iic_x, v2.0 lrb 3rh last received bit bit lrb represents the last bit (i.e. the acknowledge bit) of the last transferred byte. it is automatically cleared by a read/write access to the buffer rtb0 ? 3. note: if lrb is high (no acknowledge) in slave mode, bit trx is set automatically to select slave transmit mode. sla 2rh slave select flag 0 the iic-bus module is not addressed in slave mode, or the module is in master mode. 1 the iic-bus module has been addressed as a slave (own slave address or general address, 00 h , was received). al 1rwh arbitration lost flag bit al is set when the iic-bus module has tried to become master on the bus but has lost arbitration. operation is continued until the 9 th clock pulse. if multi-master mode is selected, the iic module temporarily switches to slave mode after a lost arbitration. bit irqp is set along with bit al. al must be cleared via software. adr 0rh address phase flag bit adr is set after a start condition in slave mode until the complete address has been received (1 byte in 7-bit address mode, 2 bytes in 10-bit address mode). field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-9 v2.2, 2004-01 iic_x, v2.0 iic_adr address control register xsfr (e606 h /--) reset value: 0000 h 1514131211109876543210 brp mod prediv - - - ica rw rw - - - rw rw rw rw field bits type description brpmod 15 rw baudrate generator mode control 0 mode 0: reciprocal divider 1 mode 1: fractional divider prediv [14:13] rw pre-divider for baudrate generation 00 pre-divider is disabled 01 pre-divider factor is 8 10 pre-divider factor is 64 11 reserved, do not use ica [9:0] rw own slave address specifies the slave address of the iic-bus module 7-bit address mode (con.m10 = 0): address stored in ica[7:1] (ica[9:8] and ica[0] are read-only, read as 0) 10-bit address mode (con.m10 = 1): address stored in ica[9:0]
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-10 v2.2, 2004-01 iic_x, v2.0 iic_cfg configuration control register xsfr (e600 h /--) reset value: 0000 h 1514131211109876543210 brp - scl en2 scl en1 scl en0 - sda en2 sda en1 sda en0 rw - rw rw rw - rw rw rw field bits type description brp [15:8] rw baudrate prescaler value determines the baudrate for the iic-bus module together with bit adr.brpmod and bitfield adr.prediv sclenx (x = 2 ? 0) 6, 5, 4 rw enable bit for sclx clock line these bits determine to which pins the iic clock line is connected. 0 sclx pin is disconnected 1 sclx pin is connected with iic clock line sdaenx (x = 2 ? 0) 2, 1, 0 rw enable bit for sdax data line these bits determine to which pins the iic data line is connected. 0 sdax pin is disconnected 1 sdax pin is connected with iic data line
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-11 v2.2, 2004-01 iic_x, v2.0 note: if bit int is set to zero and all bytes (specified in ci) of rtb0 ? 3 are read/written (dependent on bit trx), irqd will be cleared by hardware after completion of this access (this supports pec operation). iic_rtbh receive/transmit buffer high xsfr (e60a h /--) reset value: 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rtb3 rtb2 rwh rwh iic_rtbl receive/transmit buffer low xsfr (e608 h /--) reset value: 0000 h 1514131211109876543210 rtb1 rtb0 rwh rwh field bits type description rtbx (x = 3 ? 0) [31:24], [23:16], [15:8], [7:0] rwh receive/transmit buffer bytes the buffers contain the data to be sent or which have been received. the buffer size can be selected via bitfield ci, from 1 up to 4 bytes. the contents of rtb0 are sent/received first.
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-12 v2.2, 2004-01 iic_x, v2.0 20.3 iic-bus module operation the following sections describe the operation of the iic-bus module in the three different modes. in addition, detailed information on the receive/transmit buffer as well as the baudrate generator is provided. 20.3.1 operation in single-master mode in single-master mode, the iic-bus module of the XC161 is the only master controlling the external iic-bus, thus, the master can always assume that the bus is free to use. under normal conditions, there is no possibility for this master to loose arbitration. software initializes the iic-bus module according to the master operation. there is no need to specify an own slave address in register adr, as the master can never be addressed by another station. to start a transfer, the master first writes the address of the slave to be contacted (or the general call address to access all stations) into the receive/transmit buffer. in 7-bit address mode, the address is written to bitfield rtb0, bits [7:1]. in 10-bit address mode, the address is written to bitfields rtb0 and rtb1. bit 0 of rtb0 is the read/write bit r/w , which informs the slave whether the master wants to read from or write to the slave. then the master sets bit bum in register con. this generates a start condition on the bus, the busy bit bb is set, and the transmission of the buffer contents begins. to start a new transfer or to change the transfer direction, the master can generate a repeated start condition. this eliminates the need to first stop bus transactions, and then start again. the repeated start is performed by setting bit rsc in register con. the busy bit bb remains set. bit rsc is cleared automatically after the repeated start condition has been generated. when the master is finished with the current bus transaction, it generates a stop condition on the bus by clearing bit bum. 20.3.2 operation in multimaster mode in multi-master mode, the XC161 is not the only master on the bus and must share iic- bus usage with other masters. this requires bus arbitration, as only one master may control the bus at a given time. thus, when a master tries to take control of the iic-bus, it might be that the bus is already in use or that another master is trying to claim the bus at the same time. to detect such situations, each master monitors the bus activity by comparing the level which it wants to output onto the sda line with the level it reads from the external sda line. if it finds the case that it wants to output a high level (inactively driven by the master, but usually held through external pull-up devices), but the actual level on the sda line is a low level, then it recognizes this case as an ? arbitration lost ? condition, and it needs to backoff.
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-13 v2.2, 2004-01 iic_x, v2.0 it is not only necessary for the loosing master to release the bus in order to allow the other master to control the bus, but it also needs to receive the message from the other master, as it might be addressed as a slave. when the XC161 wants to use the iic-bus, it prepares to start a transfer as in single- master mode. the next recommended step is to poll bit bb to check whether the bus is busy. if bb = 0, then the start condition can be generated by setting bit bum. if the bus is still free after that, operation continues as in single-master mode. if the bus is already in use, indicated by bb = 1, the master can not take control of the bus and needs to act as a slave (acting as a slave is automatically done in hardware); bit bum should not be set in this case. if bit bum is set although the bus is already in use, the arbitration lost flag al is set. however, if testing bit bb showed that the bus is free, and software sets the bum bit, but at the same time another master tries to get onto the bus, the bus arbitration needs to take place. this is performed such that the master which first detects a mismatch between its intended output level and the actual level on the sda line looses the arbitration. the arbitration lost flag al is set in this case, the transmit selection bit trx is cleared to 0 (= reception), and the master automatically switches to slave mode to receive the address information. at the end of the address phase, hardware automatically compares the received address with the own station address stored in register adr. if the two addresses match or if the general call address (00 h ) has been received, the slave select flag sla in register st is set to indicate that the device has been contacted. operation is then continued as described in slave mode. together with bit al, the protocol event interrupt flag irqp is set, and the respective interrupt request line is activated. note that a master which has lost arbitration has written its transmit message to the receive/transmit buffer before it has tried to take control of the iic-bus. however, after it has lost arbitration, it has switched to slave mode, and was therefore receiving the message sent over the bus. this message is then stored in the receive/transmit buffer, overwriting the previous transmit message. due to the fact that a master must also act as a slave in a multi-master system, the actual implicit default operating mode in multi-master mode is slave mode. 20.3.3 operation in slave mode when the XC161 is intended to purely operate as a slave on the iic-bus, slave mode needs to be selected via bitfield mod in register con. the iic-bus module is selected by another master when it receives either its own device address or the general call address during the address phase of a transmission (the byte(s) following a start or repeated start condition). if this is the case, bit sla in register st is set, the protocol event interrupt flag irqp is set, and the respective interrupt request line is activated.
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-14 v2.2, 2004-01 iic_x, v2.0 if the device has not been selected, it remains idle in slave mode. if the device has been selected, the read/write bit r/w , which has been received together with the address information, needs to be checked by software to determine the further actions. if this bit is 0, the slave remains in receive mode, and can read the incoming message from the buffer rtb0 ? 3. if bit r/w = 1, the master wants to read from the slave device. for this, the slave needs to prepare the data to be transferred to the master. the data is written to the buffer rtb0 ? 3. writing to the buffer automatically sets the transfer mode bit trx to one (= transmission). in both cases, operation can only continue when all interrupt flags, irqd, irqe, and irqp, are cleared. otherwise, the device holds the scl clock line low to prevent further transactions on the iic-bus. in this way, a slave is able to suspend bus activities until it is ready to proceed. when a stop condition or a repeated start condition is detected, bit sla is cleared (it will be set again if the slave is contacted again at the end of the address phase of the new transaction). 20.3.4 transmit/receive buffer the iic-bus module has a transmit/receive buffer which can be set to a depth of one to four bytes. access to this buffer is performed via the two registers rtbl and rtbh, each of these represents two bytes of the buffer. the depth of the buffer is specified via bitfield ci in register con (1, 2, 3 or 4 bytes). for a transmission, the bytes to be transferred are written to the respective buffer bytes, and then transmission is initiated. the data interrupt irqd is activated when all bytes of the specified buffer have been transmitted. in receive mode, the data interrupt irqd is activated when all bytes of the specified buffer have been filled with incoming data. a byte counter, co in the status register st, counts the bytes which have been transferred from the buffer to the iic-bus or vice versa. the contents of this counter is especially of interest in slave-transmitter mode, if the bus transactions have been terminated by an external master before all bytes of the buffer have been transmitted.software can determine the number of correctly transmitted bytes by reading bitfield co. in receive mode, bitfield co needs to be read in case the transactions have been terminated (which activates the protocol event interrupt request, irqp), as it represents the number of correctly received bytes. bitfield co is always cleared to 0 by the correct number (defined by bitfield ci) of read/write accesses to the buffer registers.
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-15 v2.2, 2004-01 iic_x, v2.0 20.3.5 baud rate generation in order to give the user high flexibility in selection of cpu frequency and iic-bus baudrate without constraints to baudrate accuracy, a flexible baudrate generator has been implemented. it uses two different modes and an additional pre-divider. low baudrates may be configured at high precision in mode 0, which is compatible with previous implementations of the iic-bus module. high baudrates may be configured precisely in mode 1. figure 20-4 iic-bus module baudrate generator reciprocal divider mode (brpmod = 0) the resulting baudrate is: (20.1) table 20-1 iic-bus baudrate examples for mode 0 brpmod = 0 brp @ 100 kbit/s brp @ 400 kbit/s f iic [mhz] prediv = 00 b prediv = 01 b prediv = 00 b prediv = 01 b 40 63 h 0b h 18 h 02 h 24 3b h 06 h 0e h ? 20 31 h 05 h 0b h ? 16 27 h 04 h 09 h ? 10 18 h 02 h 05 h ? 813 h 01 h 04 h ? mca05466 prescale value brp baudrate generator circuitry b iic f iic prediv brpmod mux 64:1 8:1 b0 iic f iic 42 3 1 + () ------------------------------------------------------------------------------- =brp f iic 42 3 b0 iic ---------------------------------------------------------- - 1 ? =
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-16 v2.2, 2004-01 iic_x, v2.0 fractional divider mode (brpmod = 1) the resulting baudrate is: (20.2) 20.3.6 notes for programming the iic-bus module it is strictly recommended not to write to the iic-bus module registers while the module is busy with transfers, except when interrupt requests have been generated. in master mode (and if operating as active master in multi-master mode), the module is busy as long as the bum bit is set. in slave mode (and if operating as a slave in multi- master mode), the module is busy from a start condition (or repeated start condition) until a stop condition is detected. this is indicated by the busy bit bb. access to the module ? s registers should only be performed after appropriate interrupt requests are generated by the module, indicating a pause in or the termination of ongoing transfers. during initialization mode (mod = 00), all registers can be accessed freely. a change of the transfer direction is only allowed after a protocol interrupt. when operating as a master, software can examine the level of the acknowledge bit returned by the slave via bit lrb (last received bit) in the status register st. note that this bit represents the acknowledge bit of the last byte which was transferred before an interrupt request was generated. table 20-2 iic-bus baudrate examples for mode 1 brpmod = 1 brp @ 100 kbit/s brp @ 400 kbit/s f iic [mhz] prediv = 00 b prediv = 01 b prediv = 00 b prediv = 01 b 40 03 h 14 h 0a h 51 h 24 04 h 22 h 11 h 88 h 20 05 h 28 h 14 h a4 h 16 06 h 33 h 1a h cd h 10 0a h 51 h 29 h ? 80d h 66 h 33 h ? b1 iic f iic 1024 2 3 ------------------------------------------------ - = brp 1024 2 3 b1 iic f iic -------------------------------------------------------------------- - =
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-17 v2.2, 2004-01 iic_x, v2.0 20.4 interrupt request operation the iic-bus module can generate three different interrupt requests, each with its own request flag. however, due to the nature of these requests, it is sufficient to use only two interrupt nodes to process the requests. as the data interrupt request irqd and the end- of-data-transmission interrupt request irqe both deal with the end of a transfer of a block of data, their are combined onto one interrupt request line and node, iic_dirq, as shown in figure 20-5 . figure 20-5 iic-bus module interrupt wiring the request flags for the three possible interrupt sources are located in the status register st. the conditions for the activation of the requests and for handling of the request flags are detailed below. as long as one or more of the interrupt request flags are set, and the iic-bus module operates in master mode or has been selected as a slave, the clock line scl is held at low level to prevent further transactions on the bus. the clock line is released again when all three flags are set to 0. then, further transactions can take place on the iic bus. this operation can also be used to control iic-bus transactions by setting or clearing the request flags by software. data transfer event interrupt, irqd this request is activated and the flag is set when the specified buffer is either empty (in transmit mode) or full (in receive mode). for example, when the buffer size is set to 3 bytes (via ci) and all three buffer locations, rtb0, rtb1, and rtb2, have been written with transmit values, then the request will be activated when the last byte in rtb2 has been sent via the iic-bus. irqd is also activated in slave-transmitter mode, when a transfer was terminated by the current master before all data in the slave ? s transmit buffer has been sent. this is in addition to the activation of interrupt request irqe. if the automatic interrupt flag clear operation is selected (bit con.int = 0), then flag irqd is automatically cleared by hardware upon a complete read or write access to the buffer(s) rtb0 ? 3. if con.int = 1, then flag irqd must be cleared by software. mca05467 interrupt request circuitry >1 _ irqd irqe irqp iic_dirq iic_peirq
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-18 v2.2, 2004-01 iic_x, v2.0 end-of-data-transmission interrupt, irqe this request is activated and the flag is set when the current data transfer is terminated either by a repeated start, by a stop, or by a missing acknowledge. in the case of slave-transmitter mode, additionally the data transfer interrupt request irqd will be activated. flag irqe must be cleared by software. protocol event interrupt, irqp this request is activated and the flag is set in multi-master mode when the module has lost arbitration. additionally, the arbitration lost flag al is set. in multi-master and in slave mode, this request is activated when either the general call address or the device ? s own address has been received. flag irqp must be cleared by software. interrupt nodes the three interrupt request lines are connected to two interrupt nodes (see figure 20-5 ): note: please refer to the general interrupt control register description for an explanation of the control fields. iic_dic iic data interrupt ctrl. reg. esfr (f186 h /c3 h ) reset value: - - 00 h 1514131211109876543210 -gpx icd ir adc ie ilvl glvl - - - - - - - rw rwh rw rw rw iic_peic iic protocol intr. ctrl. reg. esfr (f18e h /c7 h ) reset value: - - 00 h 1514131211109876543210 -gpx icp ir ade ie ilvl glvl - - - - - - - rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-19 v2.2, 2004-01 iic_x, v2.0 20.5 port connection and configuration the iic-bus module can provide up to three scl/sda signal pairs, which can be connected to different pins of the XC161. the individual enable control bits for these options are located in the configuration register cfg. figure 20-6 illustrates this feature. figure 20-6 iic-bus module port pin connection options pin configuration due to the wired-and configuration of an iic-bus system, the port drivers for the scl and sda signal lines need to be operating in open-drain mode (no upper transistor). the high level on these lines are held via external pull-up devices (approx. 10 k ? for operation at 100 kbit/s, 2 k ? for operation at 400 kbit/s). all pins of the XC161 that are to be used for iic-bus communication provide open-drain drivers, and must be programmed to output operation, and their alternate function must be enabled (by setting the respective port output latch to 1), before any communication can be established. the input lines from the scl/sda pins are always connected to the iic-bus module, and do not require special programming. the inputs feature digital input filters in order to improve the rejection of noise from the external bus lines. iic bus module enable mca05468 port logic port logic port logic port logic port logic port logic sda2 sda1 sda0 scl0 scl1 scl2
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-20 v2.2, 2004-01 iic_x, v2.0 table 20-3 shows the required register setting to configure the io lines of the iic-bus module for master and slave mode operation. please note that all lines must be configured for open-drain output operation. this is required, e.g., to enable a slave module to actively hold the scl line low as long as it cannot accept further bus transactions. the iic-bus module deactivates output lines by setting the line to high level, which results in a passive level at the open-drain output. table 20-3 iic io selection and setup port lines alternate select register direction control register open drain control register bus a: p9.0 / sda0 altsel0p9.p0 = 1 and altsel1p9.p0 = x dp9.p0 = 1 odp9.p0 = 1 p9.1 / scl0 altsel0p9.p1 = 1 and altsel1p9.p1 = 0 dp9.p1 = 1 odp9.p1 = 1 bus b: p9.2 / sda1 altsel0p9.p2 = 1 and altsel1p9.p2 = 0 dp9.p2 = 1 odp9.p2 = 1 p9.3 / scl1 altsel0p9.p3 = 1 and altsel1p9.p3 = 0 dp9.p3 = 1 odp9.p3 = 1 bus c: p9.4 / sda2 altsel0p9.p4 = 1 and altsel1p9.p4 = x dp9.p4 = 1 odp9.p4 = 1 p9.5 / scl2 altsel0p9.p5 = 1 and altsel1p9.p5 = x dp9.p5 = 1 odp9.p5 = 1
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-21 v2.2, 2004-01 iic_x, v2.0 20.6 interfaces of the iic-bus module in the XC161, the iic-bus module is connected to io ports and other internal modules according to figure 20-7 . the input/output lines of the module are connected to pins of ports p9. the 2 interrupt request lines are connected to the interrupt control block. please note that two of the thee possible interrupt sources in the iic-bus module or ored together onto the request line iic_dirq (see section 20.4 ). clock control and emulation control of the iic-bus module is handled by the system control unit, scu. figure 20-7 iic-bus module io interface mca05469 port p9 control p9.1/scl0 p9.0/sda0 p9.2/sda1 p9.3/scl1 p9.4/sda2 p9.5/scl2 iic-bus module system control unit (scu) iicdis f iic interrupt control block iic_dirq sda_out [2:0] scl_out [2:0] sda_in [2:0] scl_in [2:0] iic_peirq
XC161 derivatives peripheral units (vol. 2 of 2) iic-bus module user ? s manual 20-22 v2.2, 2004-01 iic_x, v2.0 20.7 iic-bus overview figure 20-8 gives a brief overview of the major definitions of the iic-bus operation. figure 20-8 iic-bus characteristics scl sda data stable scl sda start stop scl sda transmitter sda receiver 1 st 2 nd 8 th 9 th a6 a5 a4 a0 r/w start ack bit normal data transfer start and stop conditions address and acknowledge clock synchronization scl master a scl master b external scl master arbitration scl mct05470 sda a6 a5 a4 a3 a2 master b lost arbitration master a & b master a
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-1 v2.2, 2004-01 twincan_x1, v2.1 21 twincan module 21.1 kernel description 21.1.1 overview the twincan module contains two full-can nodes operating independently or exchanging data and remote frames via a gateway function. transmission and reception of can frames is handled in accordance to can specification v2.0 part b (active). each of the two full-can nodes can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. both can nodes share the twincan module ? s resources in order to optimize the can bus traffic handling and to minimize the cpu load. the flexible combination of full-can functionality and fifo architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. improved can bus monitoring functionality as well as the increased number of message objects permit precise and comfortable can bus traffic handling. depending on the application, each of the 32 message objects can be individually assigned to one of the two can nodes. gateway functionality allows automatic data exchange between two separate can bus systems, which reduces cpu load and improves the real time behavior of the entire system. the bit timings for both can nodes are derived from the peripheral clock ( f can ) and are programmable up to a data rate of 1 mbaud. a pair of receive and transmit pins connect each can node to a bus transceiver. features can functionality according to can specification v2.0 b active. dedicated control registers are provided for each can node. a data transfer rate up to 1 mbaud is supported. flexible and powerful message transfer control and error handling capabilities are implemented. full-can functionality: 32 message objects can be individually ? assigned to one of the two can nodes, ? configured as transmit or receive object, ? participate in a 2, 4, 8, 16 or 32 message buffer with fifo algorithm, ? setup to handle frames with 11-bit or 29-bit identifiers, ? provided with programmable acceptance mask register for filtering, ? monitored via a frame counter, ? configured to remote monitoring mode. up to eight individually programmable interrupt nodes can be used. can analyzer mode for bus monitoring is implemented.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-2 v2.2, 2004-01 twincan_x1, v2.1 figure 21-1 general block diagram of the twincan module the can kernel ( figure 21-2 ) is split into a global control shell, subdivided into the initialization logic, the global control and status logic and the interrupt request compressor. ? the initialization logic sets up all submodules after power-on or reset. after finishing the initialization of the node control logic and its associated message objects, the respective can node is synchronized with the connected can bus. ? the global control and status logic informs the cpu about pending object transmit and receive interrupts and about the recent transfer history. ? the interrupt request compressor condenses the interrupt requests from 72 sources, belonging to can node a and b, to 8 interrupt nodes. a message buffer unit, containing the message buffers, the fifo buffer management, the gateway control logic and a message-based interrupt request generation unit. ? the message buffer unit stores up to 32 message objects of 8 bytes maximum data length. each object has an identifier and its own set of control and status bits. after initialization, the message buffer unit can handle reception and transmission of data without cpu supervision. ? the fifo buffer management stores the incoming and outgoing messages in a circular buffer and determines the next message to be processed by the can controller. ? the gateway control logic transfers a message from can node a to can node b or vice versa. ? the interrupt request generation unit indicates message-specifically the reception or transmission of an object. twincan module kernel mcb05471 port control txdca rxdca txdcb rxdcb can node a can node b can message object buffer twincan control clock control f can interrupt control address decoder twincan control
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-3 v2.2, 2004-01 twincan_x1, v2.1 two separate can nodes, subdivided into a bit stream processor, a bit timing control unit, an error handling logic, an interrupt request generation unit and a node control logic: ? the bit stream processor performs data, remote, error and overload frames according to the iso-dis 11898 standard. the serial data flow between the can bus line, the input/output shift register and the crc register is controlled as well as the parallel data flow between the i/o shift register and the message buffer unit. ? the bit timing control unit defines the sampling point in respect to propagation time delays and phase shift errors and performs the resynchronization. ? the error handling control logic manages the receive and the transmit error counter. according the contents in both timers, the can controller is set into an error-active, error-passive or bus-off state. ? the interrupt request generation unit signals globally the successful end of a message transmit or receive operation, all kinds of transfer problems like bit stuffing errors, format, acknowledge, crc or bit state errors, every change of the can bus warning level or of the bus-off state. ? the node control logic enables and disables the node specific interrupt sources, enters the can analyzer mode and administrates a global frame counter. figure 21-2 detailed block diagram of the twincan kernel mcb05472 interrupt request compressor global status and control logic initialization logic twincan conrtol fifo control interrupt request generation gateway control message object buffers interrupt request generation node a control logic error handling bit timing control bit stream processor to can bus a interrupt request generation error handling bit timing control bit stream processor to can bus b node b control logic
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-4 v2.2, 2004-01 twincan_x1, v2.1 21.1.2 twincan control shell 21.1.2.1 initialization processing after an external hardware reset or while it is bus-off, the respective can controller node is logically disconnected from the associated can bus and does not participate in any message transfer. this is indicated by the acr/bcr control register bit init = ? 1 ? , which is automatically set in case of a reset or while the can node is bus-off. furthermore, the can node will be disconnected by setting bit init to ? 1 ? via software. while init is active, all message transfers between the affected can node controller and its associated can bus are stopped and the bus output pin (txdc) is held on ? 1 ? level (recessive state). after an external hardware reset, all control and message object registers are reset to their associated reset values. during the bus-off-state or after a write access to register acr/bcr with init = ? 1 ? , all respective control and message object registers hold their current values (except the error counters). resetting bit init to ? 0 ? without being in the bus-off-state starts the synchronization sequence (= connection to the can bus), which has to monitor at least one bus-idle event (11 consecutive ? recessive ? bits) on the associated can bus before the node is allowed to take part in can traffic again. during the bus-off recovery sequence: the receive and the transmit error counter within the error handling logic are reset. 128 bus-idle events (11 consecutive ? recessive ? bits) have to be detected, before the synchronization sequence can be initiated. the monitoring of the bus idle events is immediately started by hardware after entering the bus-off state. the number of already detected bus-idle events is counted and indicated by the receive error counter. the reconnect procedure tests bit init by hardware after 128 bus-idle events. if init is still set, the affected can node controller waits until init is cleared and at least one bus-idle event is detected on the can bus, before the node takes part in can traffic again. if init has been already cleared, the message transfer between the affected can node controller and its associated can bus is immediately enabled.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-5 v2.2, 2004-01 twincan_x1, v2.1 21.1.2.2 interrupt request compressor the can module is equipped with 32 2 message object specific interrupt request sources and 2 4 node control interrupt request sources. a request compressor condenses these 72 sources to 8 can interrupt nodes reporting the interrupt requests of the can module. each request source is provided with an interrupt node pointer, selecting the interrupt node to start the associated service routine in order to increase flexibility in interrupt processing. each of the 8 can interrupt nodes can trigger an independent interrupt routine with its own interrupt vector and its own priority. figure 21-3 interrupt node pointer and interrupt request compressor note: all interrupts are event-oriented. the event sets the corresponding indication flag and can generate an interrupt to the system. an interrupt event occurring while its corresponding indication flag is still set, can generate a new interrupt. mca05473 >1 _ request compressor can interrupt node 0 to interrupt controller interrupt node pointer of request source k interrupt request source k >1 _ can interrupt node 7 to interrupt controller interrupt node pointer of request source n interrupt request source n
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-6 v2.2, 2004-01 twincan_x1, v2.1 21.1.2.3 global control and status logic the receive interrupt pending register rxipnd contains 32 individual flags indicating a pending receive interrupt for the associated message objects. flag rxipndn is set by hardware if the corresponding message object has correctly received a data or remote frame and the correlated interrupt request generation has been enabled by rxien = ? 10 ? . rxipndn can be cleared by software by resetting bit intpndn in the corresponding message object control register msgctrn. the transmit interrupt pending register txipnd has a similar functionality as the rxipnd register and provides identical information about pending transmit interrupts.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-7 v2.2, 2004-01 twincan_x1, v2.1 21.1.3 can node control logic 21.1.3.1 overview each node is equipped with an individual node control logic configuring the global behavior and providing status information. the configuration mode is activated when the acr/bcr register bit cce is set to ? 1 ? . this mode allows modifying the can bit timing parameters and the error counter registers. the can analyzer mode is activated when bit calm in control register acr/bcr is set to ? 1 ? . in this operation mode, data and remote frames are monitored without an active participation in any can transfer (can transmit pin is held on recessive level). incoming remote frames are stored in a corresponding transmit message object, while arriving data frames are saved in a matching receive message object. in can analyzer mode, the entire configuration information of the received frame is stored in the corresponding message object and can be evaluated by the cpu concerning their identifier, xtd bit information and data length code. if the remote monitoring mode is active by rmm = ? 1 ? , this information is also available for received remote frames. incoming frames are not acknowledged and no error frames are generated. neither remote frames are answered by the corresponding data frame nor data frames can be transmitted by setting txrq, if can analyzer mode is enabled. receive interrupts are generated (if enabled) for all correctly received frames and the respective remote pending rmtpndn is set in case of received remote frames. the node specific interrupt configuration is also defined by the node control logic via the acr/bcr register bits sie, eie and lecie: if control bit sie is set to ? 1 ? , a status change interrupt occurs when the asr/bsr register has been updated (by each successfully completed message transfer). if control bit eie is set to ? 1 ? , an error interrupt is generated when a bus-off condition has been recognized or the error warning level has been exceeded or underrun. if control bit lecie is set to ? 1 ? , a last error code interrupt is generated when an error code is set in bitfield lec in the status registers asr or bsr. the status register (asr/bsr) provides an overview about the current state of the respective twincan node: flag txok is set when a message has been transmitted successfully and acknowledged by at least one other can node, flag rxok indicates an error-free reception of a can bus message, bitfield lec indicates the last error occurred on the can bus. stuff, form, and crc errors as well as bus arbitration errors (bit0, bit1) are reported, bit ewrn is set when at least one of the error counters in the error handling logic has reached the error warning limit (default value 96),
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-8 v2.2, 2004-01 twincan_x1, v2.1 bit boff is set when the transmit error counter exceeded the error limit of 255 and the respective can node controller has been logically disconnected from the associated can bus. the can frame counter can be used to check the transfer sequence of message objects or to obtain information about the time instant, a frame has been transmitted or received from the associated can bus. can frame counting is performed by a 16-bit counter, which is controlled by register afcr/bfcr. bitfield cfcmd defines the operation mode and the trigger event incrementing the frame counter: after correctly transmitted frames, after correctly received frames, after a foreign frame on the can bus (not transmitted/received by the can node itself), at beginning of a new bit time. the captured frame counter value is copied to the cfcval field of the associated msgctrn register at the end of the monitored frame transfer. flag cfcov is set on a frame counter overflow condition (ffff h to 0000 h ) and an interrupt request is generated if bit cfcie is set to ? 1 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-9 v2.2, 2004-01 twincan_x1, v2.1 21.1.3.2 timing control unit according to iso-dis 11898 standard, a can bit time is subdivided into different segments ( figure 21-4 ). each segment consists of multiples of a time quantum t q . the magnitude of t q is adjusted by the bitfield brp and by bit div8x, both controlling the baud rate prescaler (see bit timing register abtr/bbtr). the baud rate prescaler is driven by the can module clock f can . figure 21-4 can bus bit timing standard the synchronization segment (t sync ) allows a phase synchronization between transmitter and receiver time base. the synchronization segment length is always 1 t q . the propagation time segment (t prop ) takes into account the physical propagation delay in the transmitter output driver, on the can bus line and in the transceiver circuit. for a working collision detect mechanism, t prop has to be two times the sum of all propagation delay quantities rounded up to a multiple of t q . the phase buffer segments 1 and 2 (t b1 , t b2 ) before and after the signal sample point are used to compensate a mismatch between transmitter and receiver clock phase detected in the synchronization segment. the maximum number of time quanta allowed for resynchronization is defined by bitfield sjw in bit timing register abtr/bbtr. the propagation time segment and the phase buffer segment 1 are combined to parameter t seg1 , which is defined by the value tseg1 in the respective bit timing register abtr/bbtr. a minimum of 3 time quanta is requested by the iso standard. parameter t seg2 , which is defined by the value of tseg2 in the bit timing register abtr/bbtr, covers the phase buffer segment 2. a minimum of 2 time quanta is requested by the iso standard. according iso standard, a can bit time, calculated as the sum of t sync , t seg1 and t seg2 , must not fall below 8 time quanta. note: the access to bit timing register abtr/bbtr is only enabled if bit cce in control register acr/bcr is set to ? 1 ? . mct05474 sample point transmit point sync. segment 1 bit time 1 time quantum ( t q ) t sync t prop t b1 t b1 t seg1 t seg2
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-10 v2.2, 2004-01 twincan_x1, v2.1 calculation of the bit time t q = (brp + 1) / f can , if div8x = ? 0 ? = (brp + 1) / 8 f can , if div8x = ? 1 ? t sync = 1 t q t seg1 = (tseg1 + 1) t q (min. 3 t q ) t seg2 = (tseg2 + 1) t q (min. 2 t q ) bit time = t sync + t seg1 + t seg2 (min. 8 t q ) to compensate phase shifts between clocks of different can controllers, the can controller has to synchronize on any edge from the recessive to the dominant bus level. if the hard synchronization is enabled (at the start of frame), the bit time is restarted at the synchronization segment. otherwise, the resynchronization jump width t sjw defines the maximum number of time quanta a bit time may be shortened or lengthened by one resynchronization. the value of sjw is programmed in the abtr/bbtr registers. t sjw = (sjw + 1) t q t seg1 t sjw + t prop t seg2 t sjw the maximum relative tolerance for f can depends on the phase buffer segments and the resynchronization jump width. d f can min (t b1 , t b2 ) / 2 (13 bit time - t b2 ) and d f can t sjw / 20 bit time calculation of the baudrate baudrate = f can / ((brp + 1) (1 + t seg1 + t seg2 ))
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-11 v2.2, 2004-01 twincan_x1, v2.1 21.1.3.3 bitstream processor based on the objects in the message buffer, the bitstream processor generates the remote and data frames to be transmitted via the can bus. it controls the crc generator and adds the checksum information to the new remote or data frame. after including the start of frame bit sof and the end of frame field eof, the bitstream processor starts the can bus arbitration procedure and continues with the frame transmission when the bus was found in idle state. while the data transmission is running, the bitstream processor monitors continuously the i/o line. if (outside the can bus arbitration phase or the acknowledge slot) a mismatch is detected between the voltage level on the i/o line and the logic state of the bit currently sent out by the transmit shift register, a last error interrupt request is generated and the error code is indicated by bitfield lec in status register asr/bsr. an incoming frame is verified by checking the associated crc field. when an error has been detected, the last error interrupt request is generated and the associated error code is presented in status register asr/bsr. furthermore, an error frame is generated and transmitted on the can bus. after decomposing a faultless frame into identifier and data portion, the received information is transferred to the message buffer executing remote and data frame handling, interrupt generation and status processing. 21.1.3.4 error handling logic the error handling logic is responsible for the fault confinement of the can device. its two counters, the receive error counter and the transmit error counter (control registers aecnt, becnt), are incremented and decremented by commands from the bit stream processor. if the bit stream processor itself detects an error while a transmit operation is running, the transmit error counter is incremented by 8. an increment of 1 is used, when the error condition was reported by an external can node via an error frame generation. for error analysis, the transfer direction of the disturbed message and the node, recognizing the transfer error, are indicated in the control registers aecnt, becnt. according to the values of the error counters, the can controller is set into the states error-active, error-passive or bus-off. the can controller is in error-active state, if both error counters are below the error- passive limit of 128. it is in error-passive state, if at least one of the error counters equals or exceeds 128. the bus-off state is activated if the transmit error counter equals or exceeds the bus-off limit of 256. this state is reported by flag boff in the asr/bsr status register. the device remains in this state, until the bus-off recovery sequence is finished. additionally, there is the bit ewrn in the asr/bsr status register, which is set if at least one of the error counters equals or exceeds the error warning limit defined by bitfield ewrnlvl in the control registers aecnt, becnt. bit ewrn is reset if both error counters fall below the error warning limit again.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-12 v2.2, 2004-01 twincan_x1, v2.1 21.1.3.5 node interrupt processing each can node is equipped with 4 interrupt sources supporting the global transmit/receive logic, can frame counter, error reporting system. figure 21-5 node specific interrupt control if enabled by bit sie = ? 1 ? in the acr/bcr register, the global transmit/receive logic generates an interrupt request, if the node status register (asr/bsr) is updated after finishing a faultless transmission or reception of a message object. the associated interrupt node pointer is defined by bitfield trinp in control register aginp/bginp. an error is reported by a last error code interrupt request, if activated by lecie = ? 1 ? in the acr/bcr register. the corresponding interrupt node pointer is defined by bitfield lecinp in control register aginp/bginp. the can frame counter creates an interrupt request upon an overflow, when the afcr/bfcr control register bit cfcie is set to ? 1 ? . bitfield cfcinp, located also in the aginp/bginp control register, selects the corresponding interrupt node pointer. the error logic monitors the number of can bus errors and sets or resets the error warning bit ewrn according to the value in the error counters. if bit eie in control can frame counter global can transmit and receive logic mca05475 >1 _ lecie sie >1 _ eie cfcie trinp lecinp einp cfcinp txok rxok lec ewrn boff cfcov
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-13 v2.2, 2004-01 twincan_x1, v2.1 register acr/bcr is set to ? 1 ? , an interrupt request is generated on any modification of bits ewrn and boff. the associated interrupt node pointer is defined by bitfield einp in control register aginp/bginp. 21.1.3.6 message interrupt processing each message object is equipped with 2 interrupt request sources indicating the successful end of a message transmission or reception. figure 21-6 message specific interrupt control the message based transfer interrupt sources are enabled, if bit txie or rxie in the associated message control register msgctrn are set to ? 10 ? . the associated interrupt node pointers are defined by bitfields rxinp and txinp in message configuration register msgcfgn. 21.1.3.7 interrupt indication the air/bir register provides an intid bitfield indicating the source of the pending interrupt request with the highest internal priority (lowest message object number). the type of the monitored interrupt requests, taken into account by bitfield intid, can be selected by registers aimr0/aimr4 and bimr0/bimr4 containing a mask bit for each interrupt source. if no interrupt request is pending, all bits of air/bir are cleared. the interrupt requests intpndn have to be cleared by software. mca05476 >1 _ intpnd rxipnd txipnd txie rxie transmit receive correct transfer of message object n txinp rxinp
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-14 v2.2, 2004-01 twincan_x1, v2.1 figure 21-7 intid mask for global interrupt request sources registers aimr0/4 and bimr0/4 contain a mask bit for each interrupt source (aimr0/bimr0 for message specific interrupt sources and aimr4/bimr4 for the node specific interrupt sources). if a mask bit is reset, the corresponding interrupt source is not taken into account for the generation of the intid value. figure 21-8 intid mask for message interrupt request sources mca05477 global can transmit and receive logic >1 _ txok rxok lec ewrn boff >1 _ imc34 imc33 imc32 >1 _ intd = 1 interrupt request source intid value imr4 mask register mca05478 intid = n + 2 air interrupt pending register intid = n + 2 imcn imcn intpndn bir interrupt pending register aimr0 mask register bimr0 mask register message control register for object n
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-15 v2.2, 2004-01 twincan_x1, v2.1 21.1.4 message handling unit a message object is the basic information unit exchanged between the cpu and the can controller. 32 message objects are provided by the internal can memory. each of these objects has an identifier, its own set of control and status bits and a separate data area. each message object covers 32 bytes of internal memory subdivided into control registers and data storage as illustrated in figure 21-9 . figure 21-9 structure of a message object in normal operation mode, each message object is associated with one can node. only in shared gateway mode, a message object can be accessed by both can nodes (according to the corresponding bitfield node). in order to be taken into account by the respective can node control logic, the message object must be declared valid in its associated message control register (bit msgval). when a message object is initialized by the cpu, bitfield msgval in message control register msgctrn should be reset, inhibiting a read or write access of the can node controller to the associated register and data buffer storage. afterwards, the message identifier and operation mode (transmit, receive) must be defined. if a successful transmission and/or reception of a message object should be followed by the execution of an interrupt service routine, the respective bitfields txie and rxie have to be set and the interrupt pending indicator (bitfield intpnd) should be reset. if the automatic response of an incoming remote frame with matching identifier is not requested, the respective transmission message object should be configured with cpuupd = ? 10 ? . as soon as bitfield msgval is set to ? 10 ? , the respective message object is operable and taken into account by the associated can node controller. mca05479 +18 h +14 h +10 h +0c h +08 h +00 h message object n module offset + 300 h + n*20 h fifo/gateway control message configuration message control acceptance mask arbitration (identifier) data
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-16 v2.2, 2004-01 twincan_x1, v2.1 21.1.4.1 arbitration and acceptance mask register the arbitration register msgarn is used to filter the incoming messages and to provide the outgoing messages with an identifier. the acceptance mask register msgamrn may be used to disable some identifier bits of an incoming message for the acceptance test. the identifier of a received message is compared (bitwise xor) to the identifiers of all message objects stored in the internal can controller memory. the compare operation starts at object 0 and takes into account all objects with a valid message flag (msgval = ? 10 ? ), a suitable node declaration (register msgcfgn), a cleared dir control bit (receive message object) for data frame reception, dir = ? 1 ? (transmit message object) for remote frame reception, a matching identifier length declaration (xtd = ? 1 ? marks extended 29-bit identifiers, xtd = ? 0 ? indicates standard 11 bit identifiers). the result of the compare operation is bit-by-bit anded with the contents of the acceptance mask register ( figure 21-10 ). if concordance is detected, the received message is stored into the can controller ? s message object. the compare operation is finished after analyzing message object 31. note: depending on the allocated identifiers and the corresponding mask register contents, multiple message objects may fulfill the selection criteria described above. in this case, the received frame is stored in the fitting message object with the lowest message number. figure 21-10 acceptance filtering for received message identifiers mca05480 acceptance mask of message object n result = 0: id of the received frame fits to message object n result > 0: id of the received frame does not fit to message object n =1 & identifier of message object n identifier of received frame bitwise xor bitwise and ?0? = bit match ?1? = no match
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-17 v2.2, 2004-01 twincan_x1, v2.1 21.1.4.2 handling of remote and data frames message objects can be set up for transmit or receive operation according to the selected value for control bit dir. the impact of the message object type on the associated can node controller concerning the generation or reception of remote and data frames is illustrated in table 21-1 . table 21-1 handling of remote and data frames a transmission request (txrq = ? 10 ? ) for this message object generates ? if a data frame with matching identifier is received ? if a remote frame with matching identifier is received ? receive object (receives data frames, transmits remote frames, control bit dir = ? 0 ? ) ? a remote frame. the requested data frame is stored in this message object on reception. ? the data frame is stored in this message object. ? the remote frame is not taken into account. transmit object (transmits data frames, receives remote frames, control bit dir = ? 1 ? ) ? a data frame based upon the information stored in this message object. ? the data frame is not stored. ? the remote frame is stored in this message object and rmtpnd and txrq are set to ? 10 ? . a data frame, based upon the information stored in this message object, is automatically generated if cpuupd is set to ? 01 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-18 v2.2, 2004-01 twincan_x1, v2.1 21.1.4.3 handling of transmit message objects a message object with direction flag dir = ? 1 ? (message configuration register msgcfgn) is handled as transmit object. all message objects with bitfield msgval = ? 10 ? are operable and taken into account by the can node controller operation described below. during the initialization phase, the transmit request bitfield (txrq), the new information bitfield (newdat) should be reset to ? 01 ? and the update in progress by cpu bitfield (cpuupd) in register msgctrn should be reset to ? 10 ? . the message bytes to be transmitted are written into the data partition of the message object (msgdrn0, msgdrn4). the number of message bytes to be transmitted has to be written to bitfield dlc in register msgcfgn. the selected identifier has to be written to register msgarn. then, bitfield newdat in register msgctrn should be set to ? 10 ? and bitfield cpuupd should be reset to ? 01 ? by the cpu. when the remote monitoring mode is enabled (rmm = ? 1 ? in msgcfgn), the identifier and the data length code of a received remote frame will be copied to the corresponding transmit message object, if a matching identifier was found during the compare and mask operation with all can message objects. the copy procedure may change the identifier in the transmit message object, if some msgamrn mask register bits have been set to ? 0 ? . as long as bitfield msgval in register msgctrn is set to ? 10 ? , the reception of a remote frame with matching identifier automatically sets bitfield txrq to ? 10 ? . simultaneously, bitfield rmtpnd in register msgctrn is set to ? 10 ? in order to indicate the reception of an accepted remote frame. alternatively, txrq may be set by the cpu via a write access to register msgctrn. if the transmit request bitfield txrq is found at ? 10 ? (while msgval = ? 10 ? and cpuupd = ? 01 ? ) by the appropriate can controller node, a data frame based upon the information stored in the respective transmit message object is generated and automatically transferred when the associated can bus is idle. if bitfield cpuupd in register msgctrn is set to ? 10 ? , the automatic transmission of a message object is prohibited and flag txrq is not evaluated by the respective can node controller. the cpu can release the pending transmission by clearing cpuupd. this allows the user to listen on the bus and to answer remote frames under software control. when the data partition of a transmit message object has to be updated by the cpu, bitfield cpuupd in message control register msgctrn should be set to ? 10 ? , inhibiting a read or write access of the associated can node controller. if a remote frame with an accepted identifier arrives during the update of a message object ? s data storage, bitfields txrq and rmtpnd are automatically set to ? 10 ? and the transmission of the corresponding data frame is pending until cpuupd is reset again.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-19 v2.2, 2004-01 twincan_x1, v2.1 if several valid message objects with pending transmission request are noticed by the associated can node controller, the contents of the message object with the lowest message number is transmitted first. bitfield newdat is internally reset by the respective can node controller when the contents of the selected message object ? s data registers is copied to the bitstream processor. bitfields rmtpnd and txrq are automatically reset when the message object has been successfully transmitted. the captured value of the frame counter is copied to bitfield cfcval in register msgctrn and a transmit interrupt request is generated (intpndn and txipndn are set) if enabled by txie = ? 10 ? . then the frame counter is incremented by one if enabled in control register afcr/bfcr. when a data frame with matching identifier is received, it is ignored by the respective transmit object and not indicated by any interrupt request.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-20 v2.2, 2004-01 twincan_x1, v2.1 figure 21-11 handling of message objects with direction = ? 1 ? = transmit by the can controller node hardware mca05481 matching remote frame received ? newdat := ?01? copy message to bitstream processor send message transmission successful ? no yes txrq = ?10? cpuupd = ?01? no bus free ? yes no yes txrq := ?10? rmtpnd := ?10? rxie := ?10? yes intpnd := ?10? newdat = ?10? yes no txie = ?10? yes no txrq := ?01? rmtpnd := ?01? yes intpnd := ?10? no no ?01? : reset ?10? : set
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-21 v2.2, 2004-01 twincan_x1, v2.1 21.1.4.4 handling of receive message objects a message object with direction flag dir = ? 0 ? (message configuration register msgcfgn) is handled as receive object. in the initialization phase, the transmit request bitfield (txrq), the message lost bitfield (msglst) and the newdat bitfield in register msgctr should be reset. all message objects with bitfield msgval = ? 10 ? are operable and taken into account by the can node controller operation described below. when a data frame has been received, the new information is stored in the data partition of the message object (msgdrn0, msgdrn4) and the bitfield dlc in register msgcfg is updated with the number of received bytes. unused message bytes will be overwritten by non-specified values. if the newdat bitfield in register msgctr is still set, the can controller assumes an overwrite of the previously stored message and signals a data loss by setting bitfield msglst. in any case, bitfield newdat is automatically set to ? 10 ? reporting an update of the data register by the can controller. the captured value of the frame counter is copied to bitfield cfcval in register msgctrn and a receive interrupt request is generated (intpndn and rxipndn are set) if enabled by rxie = ? 10 ? . then the frame counter is incremented by one if enabled in control register afcr/bfcr. when a receive object is marked to be transmitted (txrq = ? 10 ? ), bit msglst changes automatically to cpuupd. if cpuupd is reset to ? 01 ? , the can controller generates a remote frame which is emitted to the other communication partners via can bus. in case of cpuupd = ? 10 ? , the remote frame transfer is prohibited until the cpu releases the pending transmission by resetting cpuupd to ? 01 ? . rmtpnd and txrq are automatically reset, when the remote frame has been successfully transmitted. finally, a transmit interrupt request is generated if enabled by txie = ? 10 ? . when a remote frame with matching identifier is received, it is not answered and not indicated by an interrupt request.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-22 v2.2, 2004-01 twincan_x1, v2.1 figure 21-12 handling of message objects with direction = ? 0 ? = receive by the can controller node hardware mca05482 matching data frame received ? load identifier and control bits into bitstream processor send remote frame transmission successful ? no yes txrq = ?10? cpuupd = ?01? no bus idle ? yes no yes rxie := ?10? yes intpnd := ?10? yes txie = ?10? no txrq := ?01? rmtpnd := ?01? yes intpnd := ?10? no no newdat := ?01? newdat = ?10? no msglst := ?10? yes store message newdat := ?10? txrq := ?01? rmtpnd := ?01? ?01? : reset ?10? : set
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-23 v2.2, 2004-01 twincan_x1, v2.1 21.1.4.5 single data transfer mode the single data transfer mode is a useful feature in order to broadcast data over the can bus without unintended doubling of information. the single data transfer mode is selected via bit sdt in the fifo/gateway control register msgfgcrn. each received data frame with matching identifier is automatically stored in the corresponding receive message object if msgval is set to ? 10 ? . when data frames addressing the same message object are received within a short time interval, information might get lost (indicated by msglst = ? 10 ? ), if the cpu has not processed the former message object contents in time. each arriving remote frame with matching identifier is answered by a data frame based on the contents of the corresponding message object. this behavior may lead to multiple generation and transmission of identical data frames according to the number of accepted remote requests. if sdt is set to ? 1 ? , the can node controller automatically resets bit msgval in a message object after receiving a data frame with corresponding identifier. all following data frames, addressing the disabled message object, are ignored until msgval is set again by the cpu. if sdt is set to ? 1 ? , the can node controller automatically resets bit msgval in the addressed message object, when the transmission of the corresponding data frame has been finished successfully. in consequence, all following remote requests concerning the disabled message object are ignored until msgval is set again by the cpu. this feature allows for transmitting data in a consecutive manner without unintended doubling of any information. if sdt is cleared, control bitfield msgval is not reset by the can node controller.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-24 v2.2, 2004-01 twincan_x1, v2.1 21.1.5 can message object buffer (fifo) in case of a high cpu load, it may be difficult to process an incoming data frame before the corresponding message object is overwritten with the next input data stream provided by the can node controller. depending on the application, it could be also necessary to ensure a minimum data frame generation rate to fulfill external real time requirements. therefore, a message buffer facility has been implemented in order to avoid a loss of incoming messages and to minimize the setup time for outgoing messages. some message objects can be configured as a base object using succeeding slave message objects as individual buffer storage (building a circular buffer used as message fifo). figure 21-13 fifo buffer control structure the number of base and slave message objects, combined to a buffer, has to be a power of two (2, 4, 8 etc.) and the buffer base address has to be an integer multiple of the buffer length (e.g. a buffer containing 8 messages can use object 0, 8, 16 or 24 as base object as illustrated in table 21-2 ). a base object is defined by setting bitfield mmc to ? 010 ? in control register msgfgcrn and the requested buffer size is determined by selecting an appropriate value for fsize. a slave object is defined by setting bitfield mmc to ? 011 ? . bitfield fsize has to be equal in all fifo elements in the same fifo. mca05483 fifo object n + 7 fifo object n + 6 fifo object n + 5 fifo object n + 4 fifo object n + 3 fifo object n + 2 fifo object n + 1 fifo object n (base) protocol layer to / from can bus fifo control unit message transferred control status select object
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-25 v2.2, 2004-01 twincan_x1, v2.1 the identifiers and corresponding acceptance masks have to be identical in all fifo elements belonging to the same buffer in case of a receive fifo (dir = ? 0 ? ). in case of a transmit fifo (dir = ? 1 ? ) the identifier of the currently addressed message object is taken into account for transmission. each member of a buffer configuration keeps its individual msgval, newdat, cpuupd or msglst, txrq and rmtpnd flag and its separate interrupt control configuration. inside a fifo buffer, all elements must be assigned to the same can node (control bit node in register msgcfgn), programmed for the same transfer direction (control bit dir), set up to the same identifier length (control bit xtd), programmed to the same fifo length (bitfield fsizen) and set up with the same value for the fifo direction (bit fd in register msgfgcrn). the slave ? s canptr has to point to the fifo base object. the base object ? s canptr has to be initialized with the message number of the base object, the canptr pointers of the slave objects have to be set up with the message number of the base object. the canptr of the base object addresses the next fifo element to be accessed for information transfer and its value can be calculated according the following rule: canptrn(new) := canptrn(old) & fsizen | (canptrn(old) + 1) & fsizen control bit fd defines which transfer action (reception or transmission) leads to an update of the canptr bitfield. bit fd works independently from the direction bit dir of the fifo elements. the reception of a data frame (dir = ? 0 ? ) or the reception of a remote frame (dir = ? 1 ? ) are receive actions leading to an update of canptr if fd = ? 0 ? . the transmission of a data frame (dir = ? 1 ? ) or the transmission of a remote frame (dir = ? 0 ? ) are transmit actions initiating an increment of canptr if fd = ? 1 ? . note: the overall message object storage size is not affected by the configuration of buffer structures. the available storage size may be used for 32 message objects without buffering or for one message object with a buffer depth of 32 elements. additionally, any combination of buffered and unbuffered message objects table 21-2 message objects providing fifo base functionality msg. object n > fifo size 024681012141618 ? 30 2 stage fifo xxxxxxxxxx x 4 stage fifo x ? x ? x ? x ? x ?? 8 stage fifo x ??? x ??? x ?? 16 stage fifo x ??????? x ?? 32 stage fifo x ????????? ?
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-26 v2.2, 2004-01 twincan_x1, v2.1 according to the fifo rules is allowed as long as the limit of 32 message objects is not exceeded. 21.1.5.1 buffer access by the can controller the data transfer between the message buffer and the can bus is managed by the associated can controller. each buffer is controlled by a fifo algorithm (first in, first out = first overwritten) storing messages, delivered by the can controller, in a circular order. figure 21-14 structure of a fifo buffer with one base object and seven slave objects if the fifo buffer was initialized with receive objects, the first accepted message is stored in the base message object (number n), the second message is written to buffer element (n+1) and so on. the number of the element, used to store the next input message, is indicated by bitfield canptr in control register msgfgcrn of the base object. if the reserved buffer space has been used up, the base message object (followed by the consecutive slave objects) is addressed again to store the next incoming message. when a message object was not read out on time by the cpu, the previous mca05484 element 1 element 2 (slave) (slave) (slave) (base) (slave) (slave) (slave) (slave) element 0 element 3 element 7 element 4 element 6 element 5 can pointer = base + 2 can pointer = base + 3 can pointer = base + 1 can pointer = base + 0 can pointer = base + 5 can pointer = base + 6 can pointer = base + 4 can pointer = base + 7
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-27 v2.2, 2004-01 twincan_x1, v2.1 message data is overwritten, which is indicated by flag msglst in the corresponding msgctr register. if the fifo buffer was initialized with transmit message objects, the can controller starts the transfer with the contents of buffer element 0 (fifo base object) and increments bitfield canptr in control register msgfgcrn, pointing to the next element to be transmitted. if the message object, which is currently addressed by the base object ? s canptr, is not valid (msgval = ? 01 ? ), the fifo is not enabled for data transfer. in this case, the msgval bitfields of the other fifo elements (including the base element if not currently addressed) are not taken into account. in the case that the msgval bitfields are set to ? 10 ? for the fifo base object and ? 01 ? for the currently addressed fifo slave object, the data will not be delivered to the slave object, whereas the bitfield canptr in the fifo base object is incremented according to fifo rules. if the fifo is set up for the transmission of data frames and a matching remote frame is detected for one of the elements of the fifo, the transmit request and remote pending bits will be set automatically in the corresponding message object. the transmission of the requested data frame is handled according to the fifo rules and the value of the canptr bitfield in the fifo base object. 21.1.5.2 buffer access by the cpu the message transfer between a buffer and the cpu has to be managed by software. all message objects, combined to a buffer, can be accessed directly by the cpu. bitfield canptr in control register msgfgcrn is not automatically modified by a cpu access to the message object registers.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-28 v2.2, 2004-01 twincan_x1, v2.1 21.1.6 gateway message handling the can module supports an automatic information transfer between two independent can bus systems without cpu interaction. figure 21-15 twincan gateway functionality the gateway functionality is handled via the can message object memory shared by both can nodes. each object stored in the message memory is associated to node a or to node b via bit node in the message configuration register msgcfgn. the information exchange between both can nodes can be handled by coupling two message objects (normal gateway mode) or by sharing one common message object (shared gateway mode). in the following paragraphs, the gateway side receiving data frames is named ? source ? (indicated by ) and the side transmitting the data frames, which passed the gateway, is called ? destination ? (indicated by ). in concordance to this notation, remote frames passing the gateway are received on the destination side and transmitted on the source side. the gateway function of a message object and the requested information transfer mode are defined by bitfield mmc in the fifo/gateway control register msgfgcrn. mca05485 can message object memory bus interface gateway can node a can node b can bus a can bus b cpu
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-29 v2.2, 2004-01 twincan_x1, v2.1 figure 21-16 message burst in case of fifo/gateway 21.1.6.1 normal gateway mode the normal gateway mode consumes two message objects to transfer a message from the source to the destination node. in this mode, different identifiers can be used for the same message data. details of the message transfer through the normal gateway are controlled by the respective msgfgcr and msgfgcr registers. all 8 data bytes from the source object (even if not all bytes are valid) are copied to the destination object. the object receiving the information from the source node has to be configured as receive message object (dir = 0) and must be associated to the source can bus via bit node. register msgfgcr should be initialized according the following enumeration: bitfield mmc has to be set to ? 100 ? indicating a normal mode gateway for incoming (data) frames. bitfield canptr must be initialized with the number of the message object used as destination for the data copy process. if no fifo functionality is required on the destination side, bitfield fsize has to be filled with ? 00000 ? . when fifo capabilities are needed, bitfield fsize must contain the fifo buffer length, which has to be identical with the content of the fifo base object ? s fsize bitfield on the destination side. mca05486 message 1 message 2 message 3 message 4 destination bus speed b to fifo object n + 3 to fifo object n + 2 to fifo object n + 1 to fifo object n message 1 to fifo object n message 2 to fifo object n + 1 message 3 to fifo object n + 2 message 4 to fifo object n + 3 source bus speed a twincan node a node b
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-30 v2.2, 2004-01 twincan_x1, v2.1 when bit idc is set, the identifier of the source message object is copied to the destination message object. otherwise, the identifier of the destination message object is not modified. if dlcc is set, the data length code of the source message is copied to the destination object. bit gdfs decides, whether the transmit request flag on the destination side is set (txrq = ? 10 ? if gdfs = ? 1 ? ) after finishing the data copy process. an automatic transmission of the copied data frame on the destination side takes place, if control bit cpuupd is reset to ? 01 ? . the destination message object, addressed by canptr , has to be configured for transmit operation (dir = 1). depending on the required functionality, the destination message object can be set up in three different operating modes: with mmc = ? 000 ? , the destination message object is declared as standard message object. in this case, data frames, received on the source side, can be automatically emitted on the destination side if enabled by the respective control bits cpuupd and gdfs . remote frames, received on the destination side, are not transferred to the source side, but can be directly answered by the destination message object if cpuupd is reset to ? 01 ? . with mmc = ? 100 ? , the destination message object is declared as normal mode gateway for incoming (remote) frames. data frames, received on the source side, can be automatically emitted on the destination side if enabled (cpuupd , gdfs ) and remote frames, received on the destination side, are transmitted on the source side if enabled by srren = ? 1 ? . with mmc = ? 01x ? , the destination message object is set up as an element of a fifo buffering the data frames transferred from the source side through the gateway. remote frames, received on the destination side, are not transferred to the source side, but can be directly answered by the currently addressed fifo element if cpuupd is reset (bits srren have to be cleared). remote frame handling is completely done on the destination side according to fifo rules.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-31 v2.2, 2004-01 twincan_x1, v2.1 mmc = ? 000 ? : the operation with a standard message object on the destination side is illustrated in figure 21-17 . figure 21-17 data frame reception in normal gateway mode with a standard destination message object (mmc = ? 000 ? ) a matching data frame, arrived at the source node, is automatically copied to the destination node ? s message object addressed by canptr . bitfield canptr is loaded with the destination message object number. regardless of control bit srren , remote frames, received on the destination node, are not transferred to the source side, but can be directly answered by the destination message object. for this purpose, control bitfields txrq and rmtpnd are set to ? 10 ? , which immediately initiates a data frame transmission on the destination can bus if cpuupd is reset to ? 01 ? . mca05487 fsize = ?00000? canptr = mmc = ?100? node = dir = ?0? data id dlc txrq = ?01? rmtpnd = ?01? newdat = ?10? intpnd fsize = ?00000? canptr = mmc = ?000? node = dir = ?1? data id dlc txrq rmtpnd newdat = ?10? intpnd pointer to destination message object data frame (gdfs = ?1?) data frame copy data frame gateway destination gateway source gateway destination can bus source can bus pointer to destination message object copy if dlcc = ?1? copy copy if idc = ?1? reset reset set set if rxie = ?1? set if rxie = ?1? set unchanged set if gdfs = ?1?
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-32 v2.2, 2004-01 twincan_x1, v2.1 mmc = ? 100 ? : the operation with a normal mode gateway message object for incoming (remote) frames on the destination side is illustrated in figure 21-18 . figure 21-18 remote frame transfer in normal gateway mode, mmc = ? 100 ? the gateway object on the destination side, setup as transmit object, can receive remote frames. if bit srren in the associated gateway control register msgfgcrn is cleared, a remote frame with matching identifier is directly answered by the can destination node controller. for this purpose, control bits txrq and rmtpnd are set to ? 10 ? , which immediately initiates a data frame transmission on the destination can bus if cpuupd is reset. when bit srren is set to ? 1 ? , a remote frame received on the destination side is transferred via the gateway and transmitted again by the can source node controller. a transmit request for the gateway message object on the source side, initiated by the cpu via setting txrq , generates always a remote frame on the source can bus system. mca05488 fsize = ?00000? canptr = mmc = ?100? node = dir = ?0? data id dlc txrq rmtpnd newdat intpnd copy if idc = ?1? copy if dlcc = ?1? set if srren = ?1? set if srren = ?1? unchanged set if rxie = ?1? set if rxie = ?1? unchanged set if srren = ?0? set if srren = ?0? fsize = ?00000? canptr = mmc = ?100? node = dir = ?1? data id dlc txrq rmtpnd newdat intpnd updated if rmm = ?1? updated if rmm = ?1? pointer to source message object pointer to destination message object remote frame data frame (srren = ?0?) remote frame remote request (srren = ?1?) gateway destination gateway source gateway destination can bus source can bus
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-33 v2.2, 2004-01 twincan_x1, v2.1 21.1.6.2 normal gateway with fifo buffering mmc = ? 01x ? : when the gateway destination object is programmed as fifo buffer, bitfield canptr is used as pointer to the fifo element to be addressed as destination for the next copy process. canptr has to be initialized with the message object number of the fifo base element on the destination side. canptr is automatically updated according to the fifo rules, when a data frame was copied to the indicated fifo element on the destination side. bit gdfs determines if the txrq bit in the selected fifo element is set after reception of a data frame copied from the source side. the base message object is indicated by , the slave message objects by . the number of base and slave message objects, combined to a buffer on the destination side, has to be a power of two (2, 4, 8 etc.) and the buffer base address has to be an integer multiple of the buffer length. bitfield canptr of the fifo base element and bitfield canptr have to be initialized with the same start value (message object number of the fifo base element). canptr of all fifo slave elements must be initialized with the message object number of the fifo base element. bitfield fsize of all fifo elements must contain the fifo buffer length and has to be identical with the content of fsize . figure 21-19 illustrates the operation of a normal gateway with a fifo buffer on the destination side.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-34 v2.2, 2004-01 twincan_x1, v2.1 figure 21-19 data frame transfer in normal gateway mode with a 2 stage fifo on the destination side (mmc = ? 01x ? ) remote frames, received on the destination side by a fifo element, cannot be automatically passed to the source side. therefore, the srren control bits, associated to the fifo elements on the destination side, have to be cleared in order to answer incoming remote frames with matching identifiers directly with a data frame. buffered transfers of remote requests from the destination to the source side can be handled by a software routine operating on the fifo buffered gateway configuration for data frame transfers. the elements of the fifo buffer on the destination side should be configured as transmit message objects with cpuupd = ? 10 ? . an arriving remote fifo canptr mmc = ?011? node = mca05489 fsize = ?00001? canptr = mmc = ?100? node = dir = ?0? data id dlc txrq = ?10? rmtpnd = ?01? newdat = ?01? intpnd copy by sw if required copy by sw if required set by sw reset by sw reset by sw unchanged set if rxie = ?1? unchanged reset by sw reset by sw fsize = ?00001? canptr mmc = ?010? node = dir = ?1? data id dlc txrq = ?01? rmtpnd = ?01? newdat intpnd remote frame data frame (cpuupd = ?01?) remote frame copy remote request by sw (cpuupd = ?10?) gateway destination gateway source gateway destination can bus source can bus pointer to base object pointer to next addressed destination message object
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-35 v2.2, 2004-01 twincan_x1, v2.1 frame with matching identifier should initiate an interrupt service request for the addressed fifo message object. the associated interrupt service routine may copy the message identifier and the data length code from the received remote frame to a receive message object linked with the source side can node. in any case, txrq of the selected receive message object must be set to ? 10 ? initiating the transmission of a remote frame on the source side. figure 21-20 remote frame transfer in normal gateway mode with a 2-stage fifo on the destination side fifo canptr mmc = ?011? node = mca05490 fsize = ?00001? canptr = mmc = ?100? node = dir = ?0? data id dlc txrq = ?01? rmtpnd = ?01? newdat = ?10? intpnd copy if dlcc = ?1? reset reset set set if rxie = ?1? set if rxie = ?1? set unchanged set if gdfs = ?0? fsize = ?00001? canptr mmc = ?010? node = dir = ?1? data id dlc txrq rmtpnd newdat = ?10? intpnd data frame (gdfs = ?1?) data frame copy data frame gateway destination gateway source gateway destination can bus source can bus pointer to base object pointer to next addressed destination message object copy copy if idc = ?1?
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-36 v2.2, 2004-01 twincan_x1, v2.1 21.1.6.3 shared gateway mode in shared gateway mode, only one message object is required to implement a gateway functionality. the shared gateway object can be considered as normal message object, which is toggled between the source and destination can node as illustrated in figure 21-21 . figure 21-21 principle of the shared gateway mode each message object can be used as shared gateway by setting mmc in the corresponding msgfgcrn register to ? 101 ? . when the message configuration bit node is cleared, can node a is used as source, transferring data frames to destination node b. if node is set to ? 1 ? , can node b operates as data source. a bidirectional gateway is achieved by using a second message object, configured to shared gateway mode with a complementary node declaration. bitfield canptr has to be initialized with the shared gateway ? s message object number, whereas fsize, idc and dlcc have to be cleared. bit gdfs in control register msgfgcrn determines, whether bit txrq will be automatically set in case of an arriving data frame with matching identifier (gdfs = ? 1 ? ). mca05491 fsize = ?00000? canptr = ?n? mmc = ?101? node = dir = ?0?, ?1? data id dlc txrq rmtpnd newdat intpnd destination node source node destination can bus source can bus pointer to message object shared gateway control logic
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-37 v2.2, 2004-01 twincan_x1, v2.1 bit srren determines, whether a remote frame, received on the destination side, is transferred through the gateway to the source node or is directly answered by a data frame generated on the destination side. the functionality of the shared gateway mode is optimized to support different scenarios: a data source, connected with can node a, transmits continuously data frames, which have to be automatically emitted on the destination can bus by can node b. the corresponding transfer state transitions are 1 - 2 - ? a data source, connected with can node a, transmits continuously data frames, which have to be emitted by can node b upon a matching remote frame received from the destination can bus. the corresponding transfer state transitions are 7 - 4 - 2 - ? a data source, connected with can node a, transmits a data frame upon a matching remote frame, which has been triggered by a matching remote frame received by can node b. the respective data frame has to be emitted again on the destination can bus by can node b. the corresponding transfer state transitions are 5 - 6 - 1 - 3 - ? depending on the application, the shared gateway message object can be initialized as receive object on the source side or transmit object on the destination side via an appropriate configuration of node, dir, gdfs and srren. the various transfer states are illustrated in figure 21-22 . figure 21-22 transfer states in shared gateway mode mca05492 transmit object destination side txrq reset receive object source side txrq set 5 remote frame reception, srren = ?1? transmit object destination side txrq set receive object source side txrq reset 2 data frame transmission, srren = ?0? 1 data frame reception, gdfs = ?1? 4 remote frame reception, srren = ?0? data frame transmission, srren = ?1? remote frame transmission 6 data frame reception, gdfs = ?0? 7 3
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-38 v2.2, 2004-01 twincan_x1, v2.1 when a shared gateway message object, set up as receive object on the source side (lower left state bubble in figure 21-22 ), receives a data frame while gdfs is set to ? 1 ? , it commutes to a transmission object on the destination side by toggling control bits node and dir and sends the corresponding data frame without any cpu interaction (upper left state bubble). depending on control bit srren, the shared gateway message object returns to its initial function as receive object assigned to the source side (srren = ? 0 ? : state transition 2 to the lower left state bubble in figure 21-22 ) or remains assigned to the destination side waiting for a remote frame with matching identifier (srren = ? 1 ? : state transition 3 to the upper right state bubble). when the shared gateway message object is assigned as transmit object to the destination side (upper right state bubble), it responds to remote frames received on the destination side. if bit srren is cleared, the remote request is directly answered by a data frame based on the contents of the gateway message object (state transition 4 to the upper left state bubble). if bit srren is set and a remote frame is received on the destination side, the shared gateway message object commutes to a receive object on the source side by toggling control bits node and dir and prepares the emission of the received remote frame by setting txrq and rmtpnd to ? 10 ? (state transition 5 to the lower right state bubble). then the shared gateway message object emits the corresponding remote frame without any cpu interaction (state transition 6 to the lower left state bubble). the gateway message object remains assigned to the source side until a data frame with matching identifier arrives (lower left state bubble). then the shared gateway message object returns to the destination side and, depending on control bit gdfs, transmits immediately the corresponding data frame (gdfs = ? 1 ? , upper left state bubble) or waits upon an action of the cpu setting txrq to ? 10 ? (gdfs = ? 0 ? : state transition 7 to the upper right state bubble). alternatively, a remote frame with matching identifier, arriving on the destination side, may set txrq to ? 10 ? and initiate the data frame transmission. if a data frame arrives on the source side while the shared gateway object with matching identifier is switched to the destination side, the data frame on the source side gets lost. due to the temporary assignment to the destination node, the shared gateway message object does not notice the data frame on the source node and is not able to report the data loss via control bitfield msglst = ? 10 ? . the probability for a data loss is enlarged, if the automatic data frame transmission on the destination side is disabled by gdfs = ? 0 ? . a corresponding behavior has to be taken into account for incoming remote frames on the destination bus. note: as long as bitfield msglst is activated, an incoming data frame cannot be automatically transmitted on the destination side. due to the internal toggling of control bit dir, the shared gateway object converts from receive to transmit operation and bitfield msglst is interpreted as cpuupd = ? 10 ? preventing the automatic transmission of a data frame.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-39 v2.2, 2004-01 twincan_x1, v2.1 impact of the transfer state transitions on the bitfields in the message object in shared gateway mode: table 21-3 shared gateway state transitions (part 1 of 2) bitfields transition 1: data frame received, gdfs = ? 1 ? transition 2: data frame transmitted, srren = ? 0 ? transition 3: data frame transmitted, srren = ? 1 ? transition 4: remote frame received, srren = ? 0 ? node toggled to toggled to unchanged unchanged dir set reset unchanged unchanged data received unchanged unchanged unchanged identifier received unchanged unchanged received if rmm = ? 1 ? dlc received unchanged unchanged received if rmm = ? 1 ? txrq set reset reset set rmtpnd reset reset reset set newdat set reset reset reset intpnd set if rxie = ? 10 ? set if txie = ? 10 ? set if txie = ? 10 ? set if rxie = ? 10 ? table 21-4 shared gateway state transitions (part 2 of 2) bitfields transition 5: remote frame received, srren = ? 1 ? transition 6: remote frame transmitted transition 7: data frame received, gdfs = ? 0 ? node toggled to unchanged toggled to dir reset unchanged set data unchanged unchanged received identifier received if rmm = ? 1 ? unchanged received dlc received if rmm = ? 1 ? unchanged received txrq set reset reset rmtpnd reset reset reset newdat unchanged unchanged set intpnd set if rxie = ? 10 ? set if txie = ? 10 ? set if rxie = ? 10 ?
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-40 v2.2, 2004-01 twincan_x1, v2.1 21.1.7 programming the twincan module a software initialization should be performed by setting bit init in the can node specific control register acr/bcr to ? 1 ? . while bit init is set, all message transfers between the can controller and the can bus are disabled. the initialization routine should process the following tasks: configuration of the corresponding node, initialization of each associated message object. 21.1.7.1 configuration of can node a/b each can node can be individually configured by programming the associated register. depending on the content of the acr/bcr control registers, the normal operation mode or the can analyzer mode is activated. furthermore, various interrupt categories (status change, error, last error) can be enabled or disabled. the bit timing is defined by programming the abtr/bbtr register. the prescaler value, the synchronization jump width and the time segments, arranged before and after the sample point, depend on the characteristic of the can bus segment linked to the corresponding can node. the global interrupt node pointer register (aginp/bginp) controls multiplexer connecting an interrupt request source (error, last error, global transmit/receive and frame counter overflow interrupt request) with one of the eight common interrupt nodes. the contents of the intid mask register (aimr0/4 and bimr0/4) decides which interrupt sources may be reported by the air/bir interrupt pending register. 21.1.7.2 initialization of message objects the message memory space, containing 32 message objects, is shared by both can nodes. each message object has to be configured concerning its target node and operation properties. an initialization of the message object properties is always started with disabling the message object via msgval = ? 01 ? . the can node, associated with a message, is defined by bit node in register msgcfgn. the message object can be also defined as gateway, transferring information from can node a to b or vice versa. in this case, the fifo/gateway control register msgfgcrn must be programmed to specify the gateway mode (bitfield mmc), the target interrupt node and further details of the information handover. the identifier, correlated with a message, is set up in register msgarn. bit xtd in register msgcfgn indicates, whether an extended 29-bit or a standard 11-bit identifier is used and has to be set accordingly. incoming messages can be filtered by the mask defined in register msgamrn. the message interrupt handling can be individually configured for transmit and receive direction. the direction specific interrupt is enabled by bits txie and rxie in register msgcntn and the target interrupt node is selected by bitfields txinp and rxinp in
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-41 v2.2, 2004-01 twincan_x1, v2.1 register msgcfgn. message objects can be provided with a fifo buffer. the buffer size is determined by bitfield fsize in the fifo/gateway control register msgfgcrn. for transmit message objects, the object property assignment can be already finished by setting msgval to ? 10 ? , before the corresponding data partition has been initialized. if bitfield cpuupd is set to ? 10 ? , an incoming remote frame with matching identifier is kept in mind via setting txrq internally, but is not immediately answered by a corresponding data frame. the message data, stored in register msgdrn0/msgdrn4, can be updated as long as cpuupd is hold on ? 10 ? . as soon as cpuupd is reset to ? 01 ? , the respective data frame is transmitted by the associated can node controller. 21.1.7.3 controlling a message transfer figure 21-23 illustrates the handling of a transmit message object. the initialization of the message object properties is always started with disabling the message object via msgval = ? 01 ? . after resetting some control flags (intpnd, rmtpnd, txrq and newdat), the transfer direction and the identifier are defined. the message object initialization is finished by setting msgval to ? 10 ? . an update of a transmit message data partition should be prepared by setting cpuupd to ? 10 ? followed by a write access to the msgdrn0/msgdrn4 register. the data partition update must be indicated by the cpu via setting newdat to ? 10 ? . afterwards, bit cpuupd must be reset to ? 01 ? , if an automatic message handling is requested. in this case, the data transmission is started, when flag txrq in register msgctrn has been set to ? 10 ? by software or by the respective can node hardware due to a received remote frame with matching identifier. if cpuupd remains set, the cpu must initiate the data transmission by setting txrq to ? 10 ? and disabling cpuupd. if a remote frame with an accepted identifier arrives during the update of a message object ? s data storage, bit txrq and rmtpnd are automatically set to ? 10 ? and the transmission of the corresponding data frame is automatically started by the can controller when cpuupd is reset again. figure 21-24 demonstrates the handling of a receive message object. the initialization of the message object properties is embedded between disabling and enabling the message object via msgval as described above. after setting msgval to ? 10 ? , the transmission of a remote frame can be initiated by the cpu via txrq = ? 10 ? . the reception of a data frame is indicated by the associated can node controller via newdat = ? 10 ? . the processing of the received data frame, stored in register msgdrn0/msgdrn4, should be started by the cpu with resetting newdat to ? 01 ? . after scanning flag msglst, indicating a loss of the previous message, the received information should be copied to an application data buffer in order to release the message object for a new data frame. finally, newdat should be checked again to ensure, that the processing was based on a consistent set of data and not on a part of an old message and part of the new message.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-42 v2.2, 2004-01 twincan_x1, v2.1 figure 21-23 cpu handling of message objects with direction = transmit mca05493 want to send ? yes update message ? yes no no txrq := ?10? cpuupd := ?01? msgval = ?01? intpnd := ?01? rmtpnd := ?01? txrq := ?01? newdat := ?01? dir := ?1? (transmit object) identifier := (application specific) xtd := (application specific) txie := (application specific) rxie := (application specific) cpuupd := ?10? msgval := ?10? write / calculate message contents (all bits written with reset values) power up message initialization update : start update : end cpuupd := ?10? newdat := ?10? update ?01? : reset ?10? : set
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-43 v2.2, 2004-01 twincan_x1, v2.1 figure 21-24 cpu handling of message objects with direction = receive mca05494 newdat = ?10? ? remote frame transmission ? no no txrq := ?10? msgval = ?01? intpnd := ?01? rmtpnd := ?01? txrq := ?01? newdat := ?01? dir := 0 (receive object) msglst := ?01? txie := (application specific) rxie := (application specific) identifier := (application specific) xtd := (application specific) msgval := ?10? process message contents (all bits written with reset values) power up initialization data frame processing newdat := ?01? yes yes remote frame generation ?01? : reset ?10? : set restart process
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-44 v2.2, 2004-01 twincan_x1, v2.1 21.1.8 loop-back mode the twincan module ? s loop-back mode provides the means to internally test the twincan module and can driver software. can driver software can be developed and tested without being connected to a can bus system. in loop-back mode, the transmit pins deliver recessive signals to the transceiver. the transmit signals are combined together and are connected to the internal receive signals, as shown in figure 21-25 . the receive input pins are not taken into account in loop-back mode. figure 21-25 loop-back mode loop-back mode is controlled by bits lbm in the bit timing registers of node a and node b according to table 21-5 . table 21-5 loop-back mode abtr.lbm bbtr.lbm description 0 0 loop-back mode is disabled. 0 1 loop-back mode is disabled. 1 0 loop-back mode is disabled. 1 1 loop-back mode is enabled. mca05495 mux 1 0 1 txdcb mux 1 0 1 txdca & twincan kernel mux 0 1 mux 0 1 rxdca rxdcb lbm
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-45 v2.2, 2004-01 twincan_x1, v2.1 21.1.9 single transmission try functionality single transmission try functionality is controlled individually for each message object by bit stt in register msgfgcrn. if the single transmission try functionality is enabled, the transmit request flag txrq is reset immediately after the transmission of a frame related to this message object has started. thus, a transmit frame is only transferred once on the can bus, even if it has been corrupted by error frames. note: a message object must be tagged valid by bitfield msgval in order to enable the transmission of the respective frame.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-46 v2.2, 2004-01 twincan_x1, v2.1 21.1.10 module clock requirements the functionality of the twincan module is programmable in several respects. in order to operate at a specific baudrate with a given functionality a certain minimum module clock frequency is required. table 21-6 lists some examples for certain configurations. these examples cover the worst case conditions where the cpu executes accesses to the twincan module consecutively and with maximum speed. the module clock frequency can be reduced (see last column of table 21-6 ) if no frames without data (data frames with dlc = 0 or remote frames) are transferred over the can bus. this is possible, because internal operations can be executed while the data part is transferred. note: the given numbers are required for the maximum can bus speed of 1 mbit/s. for lower bit-rates the minimum module clock frequency can be reduced linearly, i.e. half the frequency is required for a bit-rate of 500 kbit/s. however, if two nodes are operated with different bit-rates, the module clock frequency must be chosen according to the fastest node. table 21-6 minimum module clock frequencies for 1 mbit/s 1 node active, dlc 0 2 nodes active, dlc 0 2 nodes active, dlc 1 fifo/gateway enabled 21 mhz 36 mhz 32 mhz no fifo/gateway 20 mhz 29 mhz 26 mhz
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-47 v2.2, 2004-01 twincan_x1, v2.1 21.2 twincan register description 21.2.1 register map figure 21-26 shows all registers associated with the twincan module kernel. figure 21-26 twincan kernel registers mca05496 acr asr can node a registers node a control register node a status register node a interrupt pending register node a bit timing register node a global int. node pointer reg. node a frame counter register node a intid mask register 0 node a intid mask register 4 node a error counter register msg. object n data register 0 msg. object n arbitration register msg. object n control register msg. object n fifo/gatew. cont. reg. receive interrupt pending register acr asr air abtr aginp afcr aimr0 aimr4 aecnt msgdrn0 msgarn msgctrn msgfgcrn rxipnd air abtr aginp afcr aimr0 aimr4 aecnt bcr bsr can node b registers bir bbtr bginp bfcr bimr0 bimr4 becnt msgdrn0 msgdrn4 can message object registers 1) msgarn msgamrn msgctrn msgcfgn msgfgcrn rxipnd txipnd global can control / status registers node b control register node b status register node b interrupt pending register node b bit timing register node b global int. node pointer reg. node b frame counter register node b intid mask register 0 node b intid mask register 4 node b error counter register msg. object n data register 4 msg. object n acceptance mask reg. msg. object n configuration register transmit interrupt pending register bcr bsr bir bbtr bginp bfcr bimr0 bimr4 becnt msgdrn4 msgamrn msgcfgn txipnd 1) the number ?n? indicates the message object number, n = 0 ? 31.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-48 v2.2, 2004-01 twincan_x1, v2.1 figure 21-27 twincan kernel address map ... ... reserved mca05497 +18 h fifo/gateway control message config. reg. +14 h message control reg. +10 h acceptance mask reg. +0c h arbitration register +08 h data register 4 +04 h data register 0 +00 h transmit int. pending +08 h receive int. pending +04 h +20 h error counter reg. intid mask 4 reg. +1c h intid mask 0 reg. +18 h frame counter reg. +14 h global inp reg. +10 h bit timing reg. +0c h interrupt pending reg. +08 h status reg. +04 h control reg. +00 h +20 h error counter reg. intid mask 4 reg. +1c h intid mask 0 reg. +18 h frame counter reg. +14 h global inp reg. +10 h bit timing reg. +0c h interrupt pending reg. +08 h status reg. +04 h control reg. +00 h message object 31 message object n message object 2 +6e0 h +340 h message object 1 +320 h message object 0 +300 h +2c0 h global control registers +280 h can node b registers +240 h +200 h reserved +000 h module offset node a node b can node a registers
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-49 v2.2, 2004-01 twincan_x1, v2.1 21.2.2 can node a/b registers the node control register controls the initialization, defines the node specific interrupt handling and selects an operation mode. acr node a control register reset value: 0001 h bcr node b control register reset value: 0001 h 1514131211109876543210 0 cal m cce 0 lec ie eie sie 0 init r rw rw r rw rw rw r rwh field bits type description init 0rwh initialization 0 resetting bit init starts the synchronization to the can bus. after a synchronization procedure 1) , the node takes part in can communication. 1 after setting bit init, the can node stops all can bus activities and all registers can be initialized without any impact on the actual can bus traffic. bit init is automatically set when the bus-off state is entered. sie 2rw status change interrupt enable a status change interrupt occurs when a message transfer (indicated by the flags txok or rxok in the status registers asr or bsr) is successfully completed. 0 status change interrupt is disabled. 1 status change interrupt is enabled. eie 3rw error interrupt enable an error interrupt is generated on a change of bit boff or bit ewrn in the status registers asr or bsr. 0 error interrupt is disabled. 1 error interrupt is enabled.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-50 v2.2, 2004-01 twincan_x1, v2.1 lecie 4rw last error code interrupt enable a last error code interrupt is generated when an error code is set in bitfield lec in the status registers asr or bsr. 0 last error code interrupt is disabled. 1 last error code interrupt is enabled. cce 6rw configuration change enable 0 access to bit timing register and modification of the error counters are disabled. 1 access to bit timing register and modification of the error counters are enabled. calm 7rw can analyzer mode bit calm defines if the message objects of the corresponding node operate in analyzer mode. 0 the can message objects participate in can protocol. 1 can analyzer mode is selected. 0 1, 5, [15:8] r reserved; returns ? 0 ? if read; should be written with ? 0 ? . 1) after resetting bit init by software without being in the bus-off state (e.g. after power-on), a sequence of 11 consecutive recessive bits (11 1 ? ) on the bus has to be monitored before the module takes part in the can traffic. during a bus-off recovery procedure, 128 sequences of 11 consecutive recessive bits (11 1 ? ) have to be detected. the monitoring of the recessive bit sequences is immediately started by hardware after entering the bus-off state. the number of already detected 11 1 ? sequences is indicated by the receive error counter. at the end of the bus-off recovery sequence, bit init is tested by hardware. if init is still set, the affected can node controller waits until init is cleared and 11 consecutive recessive bits (11 1 ? ) are detected on the can bus, before the node takes part in can traffic again. if init has been already cleared, the message transfer between the affected can node controller and its associated can bus is immediately enabled. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-51 v2.2, 2004-01 twincan_x1, v2.1 the node status register reports error states and successfully ended data transmissions. this register has to be read in order to release the status change interrupt request. asr node a status register reset value: 0000 h bsr node b status register reset value: 0000 h 1514131211109876543210 0 b off e wrn 0 rx ok tx ok lec r rh rh r rwh rwh rwh field bits type description lec [2:0] rwh last error code bitfield lec indicates if the latest can message transfer has been correct (no error) or it indicates the type of error, which has been detected. the error conditions are detailed in table 21-7 . 000 no error 001 stuff error 010 form error 011 ack error 100 bit1 error 101 bit0 error 110 crc error 111 reserved txok 3rwh message transmitted successfully 0 no successful transmission since last flag reset. 1 a message has been transmitted successfully (error free and acknowledged by at least one other node). txok must be reset by software. rxok 4rwh message received successfully 0 no successful reception since last flag reset. 1 a message has been received successfully. rxok must be reset by software.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-52 v2.2, 2004-01 twincan_x1, v2.1 ewrn 6rh error warning status 0 no warning limit exceeded. 1 one of the error counters in the error management logic reached the error warning limit of 96. boff 7rh bus-off status 0 can controller is not in the bus-off state. 1 can controller is in the bus-off state. 0 5, [15:8] r reserved; returns ? 0 ? if read; should be written with ? 0 ? . table 21-7 meaning of the lec bitfield lec error description no error the latest transfer on the can bus has been completed successfully. stuff error more than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. form error a fixed format part of a received frame has the wrong format. ack error the transmitted message was not acknowledged by another node. bit1 error during a message transmission, the can node tried to send a recessive level ( ? 1 ? ), but the monitored bus value was dominant (outside the arbitration field and the acknowledge slot). bit0 error two different conditions are signaled by this code: 1. during transmission of a message (or acknowledge bit, active error flag, overload flag), the can node tried to send a dominant level ( ? 0 ? ), but the monitored bus value has been recessive. 2. during bus-off recovery, this code is set each time a sequence of 11 recessive bits has been monitored. the cpu may use this code as an indication, that the bus is not continuously disturbed. crc error the crc checksum of the received message was incorrect. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-53 v2.2, 2004-01 twincan_x1, v2.1 the interrupt pending register contains the identification number of the pending interrupt request with the highest priority. air node a interrupt pending register reset value: 0000 0000 h bir node b interrupt pending register reset value: 0000 0000 h 1514131211109876543210 0intid rrwh field bits type description intid [7:0] rwh interrupt identifier 00 h no interrupt is pending. 01 h lec, ei, txok or rxok interrupt is pending. 02 h rx or tx interrupt of message object 0 is pending. 03 h rx or tx interrupt of message object 1 is pending. ?? 21 h rx or tx interrupt of message object 31 is pending. bitfield intid can be written by software to start an update after software actions and to check for changes. 0 [15:8] r reserved; returns ? 0 ? if read.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-54 v2.2, 2004-01 twincan_x1, v2.1 register aecnt/becnt contains the values of the receive error counter and the transmit error counter. some additional status/control bits allow for easier error analysis. aecnth node a error counter register high reset value: 0060 h aecntl node a error counter register low reset value: 0000 h becnth node b error counter register high reset value: 0060 h becntl node b error counter register low reset value: 0000 h 1514131211109876543210 0 le inc le td ewrnlvl rrhrh rw 1514131211109876543210 tec rec rwh rwh field bits type description rec [7:0] low rwh receive error counter bitfield rec contains the value of the receive error counter for the corresponding node. tec [15:8] low rwh transmit error counter bitfield tec contains the value of the transmit error counter for the corresponding node. ewrnlvl [7:0] low rw error warning level bitfield ewrnlvl defines the threshold value (warning level, default 60 h = 96 d ) to be reached in order to set the corresponding error warning bit ewrn.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-55 v2.2, 2004-01 twincan_x1, v2.1 note: modifying the contents of register aecnt/becnt requires bit cce = ? 1 ? in register acr/bcr. letd 8 high rh last error transfer direction 0 the last error occurred while the corresponding can node was receiving a message (rec has been incremented). 1 the last error occurred while the corresponding can node was transmitting a message (tec has been incremented). an error during message reception is indicated without regarding the result of the acceptance filtering. leinc 9 high rh last error increment 0 the error counter was incremented by 1 due to the error reported by letd. 1 the error counter was incremented by 8 due to the error reported by letd. 0 [15:10] high ? reserved; returns ? 0 ? if read; should be written with ? 0 ? . field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-56 v2.2, 2004-01 twincan_x1, v2.1 the bit timing register contains all parameters to adjust the data transfer baud rate and the bit timing. abtrh node a bit timing register high reset value: 0000 h abtrl node a bit timing register low reset value: 0000 h bbtrh node b bit timing register high reset value: 0000 h bbtrl node b bit timing register low reset value: 0000 h 1514131211109876543210 0lbm rrw 1514131211109876543210 div 8x tseg2 tseg1 sjw brp rw rw rw rw rw field bits type description brp [5:0] low rw baudrate prescaler one bit time quantum corresponds to the period length of the external oscillator clock multiplied by (brp+1), depending also on bit div8x. sjw [7:6] low rw (re)synchronization jump width (sjw+1) time quanta are allowed for resynchronization. tseg1 [11:8] low rw time segment before sample point (tseg1+1) time quanta before the sample point take into account the signal propagation delay and compensate a mismatch between transmitter and receiver clock phase. valid values for tseg1 are 2 ? 15.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-57 v2.2, 2004-01 twincan_x1, v2.1 note: modifying the contents of register abtr/bbtr requires bit cce = ? 1 ? in register acr/bcr. tseg2 [14:12] low rw time segment after sample point (tseg2+1) time quanta after the sample point take into account a user defined delay and compensate a mismatch between transmitter and receiver clock phase. valid values for tseg2 are 1 ? 7. div8x 15 low rw division of module clock f can by 8 0 the baudrate prescaler is directly driven by f can . 1 the baudrate prescaler is driven by f can /8. lbm 0 high rw loop-back mode 0 loop-back mode is disabled. 1 loop-back mode is enabled, if bits lbm are set in the btr registers of node a and node b. 0 [15:1] high r reserved; read as ? 0 ? ; should be written with ? 0 ? . field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-58 v2.2, 2004-01 twincan_x1, v2.1 the frame counter register controls the frame counter functionality and provides status information. afcrh node a frame counter register high reset value: 0000 h afcrl node a frame counter register low reset value: 0000 h bfcrh node b frame counter register high reset value: 0000 h bfcrl node b frame counter register low reset value: 0000 h 1514131211109876543210 0 cfc ov cfc ie 0cfcmd rrwhrwrrw 1514131211109876543210 cfc rwh field bits type description cfc [15:0] low rwh can frame counter this bitfield contains the count value of the frame counter. at the end of a correct message transfer, the value of cfc (captured value during sof bit) is copied to bitfield cfcval of the corresponding message object control register msgctrn.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-59 v2.2, 2004-01 twincan_x1, v2.1 cfcmd [3:0] high rw frame count mode this bitfield defines the operation mode of the frame counter. this counter can work on frame base (frame count) or on time base (time stamp). 0xxx b frame count: 1) 0xx0 b the cfc is not incremented after a foreign frame was transferred on the can bus. 0xx1 b the cfc is incremented each time a foreign frame was transferred correctly on the can bus. 0x0x b the cfc is not incremented after a frame was received by the respective can node. 0x1x b the cfc is incremented each time a frame was received correctly by the node. 00xx b the cfc is not incremented after a frame was transmitted by the node. 01xx b the cfc is incremented each time a frame was transmitted correctly by the node. 1xxx b time stamp: 1000 b the cfc is incremented with the beginning of a new bit time. the value is sampled during the sof bit. 1001 b the cfc is incremented with the beginning of a new bit time. the value is sampled during the last bit of eof. others reserved cfcie 6 high rw can frame count interrupt enable setting cfcie enables the can frame counter overflow (cfco) interrupt request. 0 the cfco interrupt is disabled. 1 the cfco interrupt is enabled. cfcov 7 high rwh can frame count overflow flag flag cfcov is set on a cfc overflow condition (ffff h to 0000 h ). an interrupt request is generated if the corresponding interrupt is enabled (cfcie = ? 1 ? ). 0 an overflow has not yet been detected. 1 an overflow has been detected since the bit has been reset. cfcov must be reset by software. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-60 v2.2, 2004-01 twincan_x1, v2.1 0 [5:4], [15:8] high r reserved; read as ? 0 ? ; should be written with ? 0 ? . 1) if the frame counter functionality has been selected (cfcmd.3 = ? 0 ? ), bit cfcmd.0 enables or disables the counting of foreign frames. a foreign frame is a correct frame on the bus, which has not been transmitted /received by the node itself. bit cfcmd.1 enables or disables the counting of frames, which have been received correctly by the corresponding can node. bit cfcmd.2 enables or disables the counting of frames, which have been transmitted correctly by the corresponding can node. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-61 v2.2, 2004-01 twincan_x1, v2.1 the global interrupt node pointer register connects each global interrupt request source with one of the 8 available can interrupt nodes. aginp node a global interrupt node pointer register reset value: 0000 h bginp node b global interrupt node pointer register reset value: 0000 h 1514131211109876543210 0 cfcinp 0 trinp 0 lecinp 0 einp r rw r rw r rw r rw field bits type description einp [2:0] rw error interrupt node pointer number of interrupt node reporting the ? error interrupt request ? , if enabled by eie = ? 1 ? . 000 b can interrupt node 0 is selected. ?? 111 b can interrupt node 7 is selected. lecinp [6:4] rw last error code interrupt node pointer number of interrupt node reporting the last error interrupt request, if enabled by lecie = ? 1 ? . 000 b can interrupt node 0 is selected. ?? 111 b can interrupt node 7 is selected. trinp [10:8] rw transmit/receive ok interrupt node pointer number of interrupt node reporting the transmit and receive interrupt request, if enabled by sie = ? 1 ? . 000 b can interrupt node 0 is selected. ?? 111 b can interrupt node 7 is selected. cfcinp [14:12] rw frame counter interrupt node pointer number of interrupt node reporting the frame counter overflow interrupt request, if enabled by cfcie = ? 1 ? . 000 b can interrupt node 0 is selected. ?? 111 b can interrupt node 7 is selected. 0 3, 7, 11, 15 ? reserved; read as ? 0 ? ; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-62 v2.2, 2004-01 twincan_x1, v2.1 the interrupt identification mask registers allow for disabling the identification notification of a pending interrupt request in the air/bir register. the interrupt mask registers aimr0/bimr0 are used to enable the message specific interrupt sources (correct transmission/ reception) for the generation of the corresponding intid value. aimrh0 node a intid mask register 0 high reset value: 0000 h aimrl0 node a intid mask register 0 low reset value: 0000 h bimrh0 node b intid mask register 0 high reset value: 0000 h bimrl0 node b intid mask register 0 low reset value: 0000 h 1514131211109876543210 imcn (n = 31-16) rw 1514131211109876543210 imcn (n = 15-0) rw field bits type description imcn (n = 15-0) imcn (n = 31-16) n low n-16 high rw message object n intid mask control 0 message object n is ignored for the generation of the intid value. 1 the interrupt pending status of message object n is taken into account for the generation of the intid value.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-63 v2.2, 2004-01 twincan_x1, v2.1 the interrupt mask registers aimr4/bimr4 are used to enable the node specific interrupt sources (last error, correct reception, error warning/bussoff) for the generation of the corresponding intid value. aimr4 node a intid mask register 4 reset value: 0000 h bimr4 node b intid mask register 4 reset value: 0000 h 1514131211109876543210 0 imc 34 imc 33 imc 32 rrwrwrw field bits type description imc32 0rw last error interrupt intid mask control 0 the last error interrupt source is ignored for the generation of the intid value. 1 the last error interrupt source is taken into account for the generation of the intid value. imc33 1rw tx/rx interrupt intid mask control 0 the tx/rx interrupt source is ignored for the generation of the intid value. 1 the tx/rx interrupt pending status is taken into account for the generation of the intid value. imc34 2rw error interrupt intid mask control 0 the error interrupt source is ignored for the generation of the intid value. 1 the error interrupt pending status is taken into account for the generation of the intid value. 0 [15:3] r reserved; read as ? 0 ? ; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-64 v2.2, 2004-01 twincan_x1, v2.1 21.2.3 can message object registers each message object is provided with a set of control and data register. the corresponding register names are supplemented with a variable n running from 0 to 31 (e.g. msgdrn0 means that data register msgdr300 is assigned with message object number 30). the message data register 0 contains the data bytes 0 to 3 of message object n. msgdrhn0 (n = 31-0) message object n data register 0 high reset value: 0000 h msgdrln0 (n = 31-0) message object n data register 0 low reset value: 0000 h 1514131211109876543210 data3 data2 rwh rwh 1514131211109876543210 data1 data0 rwh rwh field bits type description data0 [7:0] low rwh data byte 0 associated to message object n data1 [15:8] low rwh data byte 1 associated to message object n data2 [7:0] high rwh data byte 2 associated to message object n data3 [15:8] high rwh data byte 3 associated to message object n
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-65 v2.2, 2004-01 twincan_x1, v2.1 the message data register 4 contains the data bytes 4 to 7 of message object n. msgdrhn4 (n = 31-0) message object n data register 4 high reset value: 0000 h msgdrln4 (n = 31-0) message object n data register 4 low reset value: 0000 h 1514131211109876543210 data7 data6 rwh rwh 1514131211109876543210 data5 data4 rwh rwh field bits type description data4 [7:0] low rwh data byte 4 associated to message object n data5 [15:8] low rwh data byte 5 associated to message object n data6 [7:0] high rwh data byte 6 associated to message object n data7 [15:8] high rwh data byte 7 associated to message object n
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-66 v2.2, 2004-01 twincan_x1, v2.1 register msgarn contains the identifier of message object n. msgarhn (n = 31-0) message object n arbitration register high reset value: 0000 h msgarln (n = 31-0) message object n arbitration register low reset value: 0000 h 1514131211109876543210 0 id[28:16] rrwh 1514131211109876543210 id[15:0] rwh field bits type description id[15:0] id[28:16] [15:0] low [12:0] high rwh message identifier identifier of a standard message (id[28:18]) or an extended message (id[28:0]). for standard identifiers bits id[17:0] are ? don ? t care ? . 0 [15:13] high r reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-67 v2.2, 2004-01 twincan_x1, v2.1 register msgamrn contains the mask bits for the acceptance filtering of message object n. msgamrhn (n = 31-0) message object n arbitration mask register high reset value: ffff h msgamrln (n = 31-0) message object n arbitration mask register low reset value: ffff h 1514131211109876543210 1 am[28:16] rrw 1514131211109876543210 am[15:0] rw field bits type description am[15:0] am[28:16] [15:0] low [12:0] high rw message acceptance mask mask to filter incoming messages with standard identifiers (am[28:18]) or extended identifiers (am[28:0]). for standard identifiers bits am[17:0] are ? don ? t care ? . 0 identifier bit is ignored for acceptance test. 1 identifier bit is taken into account for the acceptance filtering. 1 [15:13] high r reserved; returns ? 1 ? if read; should be written with ? 1 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-68 v2.2, 2004-01 twincan_x1, v2.1 register msgctrn affects the data transfer between a can node controller and the corresponding message object n and provides a bitfield to store the captured value of the frame counter. msgctrhn (n = 31-0) message object n message control register high reset value: 0000 h msgctrln (n = 31-0) message object n message control register low reset value: 5555 h 1514131211109876543210 cfcval rwh 1514131211109876543210 rmtpnd txrq msglst cpuupd newdat msgval txie rxie intpnd rwh rwh rwh rwh rwh rw rw rwh field bits type description intpnd [1:0] low rwh message object interrupt pending intpnd is generated by an ? or ? operation between the rxipndn and txipndn flags (if enabled by txie or rxie). intpnd must be reset by software. resetting intpnd also resets the corresponding rxipnd and txipnd flags. 01 no message object interrupt request is pending. 10 the message object has generated an interrupt request. rxie [3:2] low rw message object receive interrupt enable 01 message object receive interrupt is disabled. 10 message object receive interrupt is enabled. if rxie is set, bits intpnd and rxipnd are set after successful reception of a frame. txie [5:4] low rw message object transmit interrupt enable 01 message object transmit interrupt is disabled. 10 message object transmit interrupt is enabled. if txie is set, bits intpnd and txipnd are set after successful transmission of a frame.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-69 v2.2, 2004-01 twincan_x1, v2.1 msgval 1) [7:6] low rwh message object valid the can controller only operates on valid message objects. message objects can be tagged invalid while they are changed or if they are not used at all. 01 message object is invalid. 10 message object is valid. newdat 2) [9:8] low rwh new message object data available 01 no update of message object data occurred. 10 new message object data has been updated. msglst [11:10] low rwh message lost (for reception only) 01 no message object data is lost. 10 the can controller has stored a new message into the message object while newdat was still set. the previously stored message is lost. msglst must be reset by software. cpuupd 3) [11:10] low rwh cpu update (for transmission only) indicates that the corresponding message object can not be transmitted now. the software sets this bit in order to inhibit the transmission of a message that is currently updated by the cpu or to control the automatic response to remote requests. 01 the message object data can be transmitted automatically by the can controller. 10 the automatic transmission of the message data is inhibited. txrq 4) [13:12] low rwh message object transmit request flag 01 no message object data transmission is requested by the cpu or a remote frame. 10 the transmission of the message object data, requested by the cpu or by a remote frame, is pending. automatic setting of txrq by the can node controller can be disabled for gateway message objects via control bit gdfs = ? 0 ? . txrq is automatically reset, when the message object has been successfully transmitted. if there are several valid message objects with pending transmit requests, the message object with the lowest message number will be transmitted first. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-70 v2.2, 2004-01 twincan_x1, v2.1 note: for transmitting frames (remote frames or data frames), bitfield cpuupd/msglst has to be reset. rmtpnd [15:14] low rwh remote pending flag (used for transmit-objects) 01 no remote node request for a message object data transmission. 10 transmission of the message object data has been requested by a remote node but the data has not yet been transmitted. when rmtpnd is set, the can node controller also sets txrq. rmtpnd is automatically reset, when the message object data has been successfully transmitted. cfcval [15:0] high rwh message object frame counter value cfcval contains a copy of the frame counter content valid for the last correct data transmission or reception executed for the corresponding message object. 1) msgval has to be set from ? 01 ? to ? 10 ? in order to take into account an update of bits xtd, dir, node and canptr. 2) bit newdat indicates that new data has been written into the data registers of this corresponding message object. for transmit objects, newdat should be set by software and is reset by the respective can node controller when the transmission is started. for receive objects, newdat is set by the respective can node controller after receiving a data frame with matching identifier. it has to be reset by software. when the can controller writes new data into the message object, unused message bytes will be overwritten with non-specified values. usually, the cpu will clear this bitfield before working on the data and will verify that the bitfield is still cleared once the cpu has finished working to ensure a consistent set of data. for transmit objects, the cpu should set this bitfield along with clearing bitfield cpuupd. this will ensure that, if the message is actually being transmitted during the time the message is updated by the cpu, the can controller will not reset bitfield txrq. in this way, txrq is only reset once the actual data has been transferred correctly. 3) while bitfield msgval is set ( ? 10 ? ) an incoming matching remote frame is taken into account by automatically setting bitfields txrq and rmtpnd to ? 10 ? (independent from bitfield cpuupd/msglst). the transmission of a frame is only possible if cpuupd is reset ( ? 01 ? ). 4) if a receive object (dir = ? 0 ? ) is requested for transmission, a remote frame will be sent in order to request a data frame from another node. if a transmit object (dir = ? 1 ? ) is requested for transmission, a data frame will be sent. bitfield txrq will be reset by the can controller along with bitfield rmtpnd after the correct transmission of the data frame if bitfield newdat has not been set or after correct transmission of a remote frame. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-71 v2.2, 2004-01 twincan_x1, v2.1 the control and status element of the message control registers is implemented with two complementary bits (except the frame counter value). this special mechanism allows the selective setting or resetting of a specific element (leaving others unchanged) without requiring read-modify-write cycles. table 21-8 illustrates how to use these 2-bitfields. register msgcfgn defines the configuration of message object n and the associated interrupt node pointers. changes of bits xtd, node or dir by software are only taken into account after setting bitfield msgval to ? 10 ? . this avoids unintentional modification while the message object is still active by explicitly defining a timing instant for the update. bits xtd, node or dir can be written while msgval is ? 01 ? or ? 10 ? , the update always takes place by setting msgval to ? 10 ? . table 21-8 setting/resetting the control and status element of the message control registers value of the 2-bitfield function on write meaning on read 00 b reserved reserved 01 b reset element element is reset 10 b set element element is set 11 b leave element unchanged reserved msgcfghn (n = 31-0) message object n message configuration register high reset value: 0000 h msgcfgln (n = 31-0) message object n message configuration register low reset value: 0000 h 1514131211109876543210 0 txinp 0 rxinp rrwrrw 1514131211109876543210 0 dlc dir xtd no de rmm rrwhrwhrwrwhrw
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-72 v2.2, 2004-01 twincan_x1, v2.1 field bits type description rmm 0 low rw transmit message object remote monitoring mode 0 remote monitoring mode is disabled. 1 remote monitoring mode is enabled for this transmit message object. the identifier and dlc code of a remote frame with matching identifier are copied to this transmit message object in order to monitor incoming remote frames. bit rmm is only available for transmit objects and has no impact for receive objects. node 1 low rwh message object can node select 0 the message object is assigned to can node a. 1 the message object is assigned to can node b. xtd 2 low rw message object extended identifier 0 this message object uses a standard 11-bit identifier. 1 this message object uses an extended 29-bit identifier. dir 3 low rwh message object direction control 0 the message object is defined as receive object. if txrq = ? 10 ? , a remote frame with the identifier of this message object is transmitted. on reception of a data frame with matching identifier, the message data is stored in the corresponding msgdrn0/msgdrn4 registers. 1 the message object is declared as transmit object. if txrq = ? 10 ? , the respective data frame is transmitted. on reception of a remote frame with matching identifier, rmtpnd and txrq are set to ? 10 ? . dlc 1) [7:4] low rwh message object data length code 0000 b - 1xxx b dlc contains the number of data bytes associated to the message object. bitfield dlc may be modified by hardware in remote monitoring mode and in gateway mode.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-73 v2.2, 2004-01 twincan_x1, v2.1 the fifo/gateway control register msgfgcrn contains bits to enable and to control the fifo functionality, the gateway functionality and the desired transfer actions. rxinp [2:0] high rw receive interrupt node pointer bitfield rxinp determines which interrupt node is triggered by a message object receive event, if bitfield rxie in register msgctrn is set. 000 b can interrupt node 0 is selected. ?? 111 b can interrupt node 7 is selected. txinp [6:4] high rw transmit interrupt node pointer bitfield txinp determines which interrupt node is triggered by a message object transmit event, if bitfield txie in register msgctrn is set. 000 b can interrupt node 0 is selected. ?? 111 b can interrupt node 7 is selected. 0 [15:8] low 3, [15:7] high r reserved; returns ? 0 ? if read; should be written with ? 0 ? . 1) the maximum number of data bytes is 8. a value > 8 written by the cpu, is internally corrected to 8 but the content of bitfield dlc is not updated. if a received data frame contains a data length code value > 8, only 8 bytes are taken into account. a read access to bitfield dlc returns the original value of the dlc field of the received data frame. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-74 v2.2, 2004-01 twincan_x1, v2.1 msgfgcrhn (n = 31-0) message object n fifo/gateway control register high reset value: 0000 h msgfgcrln (n = 31-0) message object n fifo/gateway control register low reset value: 0000 h 1514131211109876543210 0 mmc 0 canptr rrwrrwh 1514131211109876543210 stt sdt fd 0 dl cc idc srr en gd fs 0fsize rw rw rw r rw rw rw rw r rw field bits type description fsize [4:0] low rw fifo size control bitfield fsize determines the number of message objects combined to a fifo buffer. even numbered message objects may provide fifo base or slave functionality, while odd numbered message objects are restricted to slave functionality. in gateway mode, fsize determines the length of the fifo on the destination side. 00000 b message object n is part of a 1-stage fifo 00001 b message object n is part of a 2-stage fifo 00011 b message object n is part of a 4-stage fifo 00111 b message object n is part of a 8-stage fifo 01111 b message object n is part of a 16-stage fifo 11111 b message object n is part of a 32-stage fifo else reserved fsize = ? 00000 ? leads to the behavior of a standard message object (the pointer canptr used for this action will not be changed). this value has to be written if a gateway transfer to a single message object (no fifo) as destination is desired. fsize is not evaluated for message objects configured in standard mode, shared gateway mode or fifo slave functionality. in this case, fsize should be programmed to ? 00000 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-75 v2.2, 2004-01 twincan_x1, v2.1 gdfs 8 low rw gateway data frame send specifies if a can data frame will be automatically generated on the destination side after new data has been transferred via gateway from the source to the destination side. 0 no additional action, txrq will not be set on the destination side. 1 the corresponding data frame will be sent automatically (txrq of the message object, pointed to by canptrn, will be set by hardware). bit gdfs is only taken into account, if a data frame has been received (dir = ? 0 ? ). srren 9 low rw source remote request enable specifies if the transmit request bit is set in message object n itself (to generate a data frame) or in the message object pointed to by canptrn (in order to generate a remote frame on the source bus). 0 a remote on the source bus will not be generated, a data frame with the contents of the destination object will be generated on the destination bus, instead (txrqn will be set). 1 a data frame with the contents of the destination object will not be sent. instead, a corresponding remote frame will be generated by the message object pointed to by bitfield canptrn (txrq[canptrn] will be set). srren is restricted to transmit message objects in normal or shared gateway mode (dir = ? 1 ? ). this bit is only taken into account if a remote frame has been received. bit srren must not be set if message object n is part of a fifo buffer. in order to generate a remote frame on the source side, canptr has to point to the source message object. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-76 v2.2, 2004-01 twincan_x1, v2.1 idc 10 low rw identifier copy idc controls the identifier handling during a frame transfer through a gateway. 0 the identifier of the receiving object is not copied to the transmitting message object. 1 the identifier of the receiving object is automatically copied to the transmitting message object. bitfield idc is restricted to message objects configured in normal gateway mode. dlcc 11 low rw data length code copy dlcc controls the handling of the data length code during a data frame transfer through a gateway. 0 the data length code, provided by the source object, is not copied to the transmitting object. 1 the data length code, valid for the receiving object, is copied automatically to the transmitting object. bitfield dlcc is restricted to message objects configured in normal gateway mode. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-77 v2.2, 2004-01 twincan_x1, v2.1 fd 13 low rw fifo direction fd is only taken into account for a fifo base object (the fd bits of all fifo elements should have an identical value). it defines which transfer action (reception or transmission) leads to an update of the fifo base object ? s canptr. 0 fifo reception: the canptr (of the fifo base object) is updated after a correct reception of a data frame (dir = ? 0 ? ) or a remote frame (dir = ? 1 ? ) by the currently addressed message object. the canptr is left unchanged after any transmission. 1 fifo transmission: the canptr (of the fifo base object) is updated after a correct transmission of a data frame (dir = ? 1 ? ) or a remote frame (dir = ? 0 ? ) from the currently addressed message object. the canptr is left unchanged after any reception. bitfield fd is not correlated with bit dir. sdt 14 low rw single data transfer mode this bit is taken into account in any transfer mode (fifo mode or as standard object, receive and transmit objects). 0 control bit msgval is not reset when this object has taken part in a successful data transfer (receive or transmit). 1 control bit msgval is automatically reset after a successful data transfer (receive or transmit) has taken place. bit sdt is not taken into account for remote frames. bit sdt has to be reset in all message objects belonging to a fifo buffer. stt 15 low rw single transmission try 0 single transmission try is disabled. 1 single transmission try is enabled. the corresponding txrq bit is reset immediately after the transmission has started 1) . field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-78 v2.2, 2004-01 twincan_x1, v2.1 canptr [4:0] high rwh can pointer for fifo/gateway functions message object is configured in standard mode (mmc = ? 000 ? ): no impact, canptr should be initialized with the respective message object number. message object is configured as fifo base object (mmc = ? 010 ? ): canptr contains the number of the message object addressed by the associated can controller for the next transmit or receive operation. for initialization, canptr should be written with the message number of the respective fifo base object. message object is configured as fifo slave object (mmc = ? 011 ? ): canptr has to be initialized with the respective message object number of the fifo base object. message object is configured for normal gateway mode (mmc = ? 100 ? ): canptr contains the number of the message object used as gateway destination object. message object is configured as gateway destination object without fifo functionality (mmc = ? 000 ? ): if srren is set to ? 1 ? , canptr has to be initialized with the number of the message object used as gateway source. the backward pointer is required to transfer remote frames from the destination to the source side. if srren is cleared, canptr is not evaluated and must be initialized with the respective message object number. message object is configured for shared gateway mode (mmc = ? 101 ? ): no impact, canptr has to be initialized with the respective message object number. for fifo functionality (or gateway functionality with a fifo as destination), canptrn should not be written by software while fifo mode is activated and data transfer is in progress. this bitfield can be used to reset the fifo by software. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-79 v2.2, 2004-01 twincan_x1, v2.1 note: changes of bitfield canptr for transmission objects are only taken into account after setting bitfield msgval to ? 10 ? . this avoids unintentional modification while the message object is still active by explicitly defining a timing instant for the update. bitfield canptr for transmission objects can be written while msgval is ? 01 ? or ? 10 ? , the update always takes place by setting msgval to ? 10 ? . changes of bitfield canptr for receive objects are immediately taken into account. mmc [10:8] high rw message object mode control bitfield mmc controls the functionality of message object n. 000 b standard message object functionality 010 b fifo functionality enabled (base object) 011 b fifo functionality enabled (slave object) 100 b normal gateway functionality for incoming frames 101 b shared gateway functionality for incoming frames others reserved 0 [7:5], 12 low [7:5], [15:11] high ? reserved; returns ? 0 ? if read; should be written with ? 0 ? . 1) as a result, a message will not be re-transmitted if it has lost arbitration or has been corrupted by an error frame. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-80 v2.2, 2004-01 twincan_x1, v2.1 21.2.4 global can control/status registers the receive interrupt pending register indicates the pending receive interrupts for message object n. rxipndh receive interrupt pending register high reset value: 0000 h rxipndl receive interrupt pending register low reset value: 0000 h 1514131211109876543210 rxipndn (n = 31-16) rh 1514131211109876543210 rxipndn (n = 15-0) rh field bits type description rxipndn (n = 15-0) rxipnd (n = 31-16) n low n-16 high rh message object n receive interrupt pending bit rxipndn is set by hardware if message object n received a frame and bit rxien has been set. 0 no receive is pending for message object n. 1 receive is pending for message object n. rxipndn can be cleared by software via resetting the corresponding bit intpndn.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-81 v2.2, 2004-01 twincan_x1, v2.1 the transmit interrupt pending register indicates whether a transmit interrupt is pending for message object n. txipndh transmit interrupt pending register high reset value: 0000 h txipndl transmit interrupt pending register low reset value: 0000 h 1514131211109876543210 txipndn (n = 31-16) rh 1514131211109876543210 txipndn (n = 15-0) rh field bits type description txipndn (n = 15-0) txipnd (n = 31-16) n low n-16 high rh message object n transmit interrupt pending bit txipndn is set by hardware if message object n transmitted a frame and bit txien has been set. 0 no transmit is pending for message object n. 1 transmit is pending for message object n. txipndn can be cleared by software via resetting the corresponding bit intpndn.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-82 v2.2, 2004-01 twincan_x1, v2.1 21.3 XC161 module implementation details this section describes: the twincan module related interfaces such as port connections and interrupt control all twincan module related registers with its addresses and reset values 21.3.1 interfaces of the twincan module in XC161 the twincan module is connected to io ports according to figure 21-28 . figure 21-28 twincan module io interface the input receive pins can be selected by bitfield risa (for node a) and bitfield risb (for node b) in the pisel register. the output transmit pins are defined by the corresponding altsel registers of port 4, port 7, or port 9. the twincan has eight interrupt request lines. note: the interrupt node of interrupt request 7 of the twincan can be shared with the sdlm module. port 9 control mca05498 interrupt control can0int can5int can1int can2int can3int can4int can7int can6int address decoder twincan module (kernel) f can p9.2 p9.3 p9.1 p9.0 altsel p4.6 p4.7 p4.5 p4.4 port 4 control altsel port 7 control p7.6 p7.7 p7.5 p7.4 altsel p9.3_tx mux rxdca p9.2_rx p9.1_tx p9.0_rx p7.7_tx p7.5_tx p7.6_rx p7.4_rx p4.7_rx p4.7_tx p4.6_tx p4.5_rx p4.4_rx mux rxdcb pisel 33 txdcb txdca
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-83 v2.2, 2004-01 twincan_x1, v2.1 21.3.2 twincan module related external registers figure 21-29 shows the module related external registers which are required for programming the twincan module. figure 21-29 twincan implementation specific registers mca05499 altsel0p4 dp4 port registers altsel0p7 dp7 altsel0p9 dp9 can_0ic can_1ic interrupt registers can_2ic can_3ic can_4ic can_5ic can_pisel system registers can_6ic can_7ic
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-84 v2.2, 2004-01 twincan_x1, v2.1 21.3.2.1 system registers register can_pisel allows the user to select the input pins for the two twincan receive signals rxdca and rxdcb. can_pisel twincan port input select register reset value: 0000 h 1514131211109876543210 0 risb risa rrwrw field bits type description risa [2:0] rw receive input selection for node a bitfield risa defines the input pin for the twincan receive line rxdca for node a. 000 the input pin for rxdca is p4.5 001 the input pin for rxdca is p4.7 010 the input pin for rxdca is p7.6 011 the input pin for rxdca is p9.2 1xx reserved. risb [5:3] rw receive input selection for node b bitfield risb defines the input pin for the twincan receive line rxdcb for node b. 000 the input pin for rxdcb is p4.4 001 the input pin for rxdcb is p9.0 010 the input pin for rxdcb is p7.4 011 reserved. 1xx reserved. 0 [15:6] r reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-85 v2.2, 2004-01 twincan_x1, v2.1 21.3.2.2 port registers the port registers required to program to twincan operation are listed as follows. altsel0p4 p4 alternate select register 0 reset value: 0000 h 1514131211109876543210 0p7p6 0 r rw rw r field bit type description altsel0 p4.y 6, 7 rw p4 alternate select register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function dp4 p4 direction ctrl. register reset value: 0000 h 1514131211109876543210 0p7p6p5p4 p3 p2 p1 p0 r rw rw rw rw rw rw rw rw field bit type description dp4.y 7 ? 4rw port direction register dp4 bit y 0 port line p4.y is an input (high-impedance) 1 port line p4.y is an output
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-86 v2.2, 2004-01 twincan_x1, v2.1 note: shaded bits are not related to twincan operation. altsel0p7 p7 alternate select register 0 reset value: 0000 h 1514131211109876543210 0p7 0p5 0 0 r rw rw rw rw r field bit type description altsel0 p7.y 7, 5 rw p7 alternate select register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function dp7 p7 direction ctrl. register reset value: 0000 h 1514131211109876543210 0p7p6p5p4 0 r rw rw rw rw r field bit type description dp7.y 7 ? 4rw port direction register dp7 bit y 0 port line p7.y is an input (high-impedance) 1 port line p7.y is an output
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-87 v2.2, 2004-01 twincan_x1, v2.1 altsel0p9 p9 alternate select register 0 reset value: 0000 h 1514131211109876543210 0 0 0p3 0p1 0 r rw rw rw rw rw rw field bit type description altsel0 p9.y 3, 1 rw p9 alternate select register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function altsel1p9 p9 alternate select register 1 reset value: 0000 h 1514131211109876543210 0 0 0p3 0p1 0 r rw rw rw rw rw rw field bit type description altsel1 p9.y 3, 1 rw p9 alternate select register 1 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-88 v2.2, 2004-01 twincan_x1, v2.1 note: shaded bits are not related to twincan operation. dp9 p9 direction ctrl. register reset value: 0000 h 1514131211109876543210 0 p5 p4 p3 p2 p1 p0 r rw rw rw rw rw rw field bit type description dp9.y 3 ? 0rw port direction register dp9 bit y 0 port line p9.y is an input (high-impedance) 1 port line p9.y is an output
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-89 v2.2, 2004-01 twincan_x1, v2.1 table 21-9 shows the required register setting to configure the io lines of the twincan module for operation. note: the altsel1 registers of port 7 and port 4 are ? don ? t care ? for selecting the twincan alternate output function. table 21-9 twincan io selection and setup port lines alternate select register port input select register direction control register io twincan node a p4.5 / rxdca ? can_pisel[2:0] = 000 dp4.p5 = 0 input p4.6 / txdca altsel0p4.p6 = 1 ? dp4.p6 = 1 output p4.7 / rxdca ? can_pisel[2:0] = 001 dp4.p7 = 0 input p7.6 / rxdca ? can_pisel[2:0] = 010 dp7.p6 = 0 input p7.7 / txdca altsel0p7.p7 = 1 ? dp7.p7 = 1 output p9.2 / rxdca ? can_pisel[2:0] = 011 dp9.p2 = 0 input p9.3 / txdca altsel0p9.p3 = 1 and altsel1p9.p3 =1 ? dp9.p3 = 1 output twincan node b p4.4 / rxdcb ? can_pisel[5:3] = 000 dp4.p4 = 0 input p4.7 / txdcb altsel0p4.p7 = 1 ? dp4.p7 = 1 output p7.4 / rxdcb ? can_pisel[5:3] = 010 dp7.p4 = 0 input p7.5 / txdcb altsel0p7.p5 = 1 ? dp7.p5 = 1 output p9.0 / rxdcb ? can_pisel[5:3] = 001 dp9.p0 = 0 input p9.1 / txdcb altsel0p9.p1 = 1 and altsel1p9.p1 =1 ? dp9.p1 = 1 output
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-90 v2.2, 2004-01 twincan_x1, v2.1 21.3.2.3 interrupt registers the interrupts of the twincan module are controlled by the following interrupt control registers: can_0ic can_1ic can_2i can_3i can_4i can_5ic can_6ic can_7ic all interrupt control registers have the same structure. refer to the system units for its description and also details on interrupt handling and processing.
XC161 derivatives peripheral units (vol. 2 of 2) twincan module user ? s manual 21-91 v2.2, 2004-01 twincan_x1, v2.1 21.3.3 register table table 21-10 shows the system registers related to the twincan module. it summarizes the addresses and reset values. in order to simplify the kernel description, the prefix ? can_ ? is added only in this register list. the start address for the twincan module is 20 ? 0000 h , the register offsets (relative to this address) are given in the twincan kernel description. see figure 21-27 . a full register listing of all can registers is provided in register table section and in the system book. table 21-10 twincan module register summary name description address 1) 1) the 8-bit short addresses are not available for the twincan module kernel registers. reset value 16-bit twincan module system registers can_pisel twincan port input select register 20 ? 0004 h 0000 h can_0ic twincan interrupt control register for the can interrupt node 0. f196 h 0000 h can_1ic twincan interrupt control register for the can interrupt node 1. f142 h 0000 h can_2ic twincan interrupt control register for the can interrupt node 2. f144 h 0000 h can_3ic twincan interrupt control register for the can interrupt node 3. f146 h 0000 h can_4ic twincan interrupt control register for the can interrupt node 4. f148 h 0000 h can_5ic twincan interrupt control register for the can interrupt node 5. f14a h 0000 h can_6ic twincan interrupt control register for the can interrupt node 6. f14c h 0000 h can_7ic 2) 2) in the XC161 device, the can interrupt node 7 is shared with the sdlm interrupt 1. in order to avoid mismatches if the can interrupt 7 is used by the twincan module, the sdlm interrupt 1 should be mapped to a common sdlm interrupt 0 (see register sdlm_pisel). twincan interrupt control register for the can interrupt node 7. f14e h 0000 h
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-1 v2.2, 2004-01 sdlm_x, v2.0 22 serial data link module sdlm 22.1 overview the serial data link module (sdlm) provides serial communication to a j1850 based multiplexed bus via an external j1850 bus transceiver chip. the module is conform to the sae class b j1850 specification and compatible to class 2 protocol. general sdlm features compliant to sae class b j1850 specification gm class 2 protocol fully supported variable pulse width (vpw) format with 10.4 kbaud high speed receive/transmit 4x mode with 41.6 kbaud digital noise filter power save mode and automatic walk-up upon bus activity single-byte headers or consolidated headers supported crc generation & check supported receive and transmit block mode supported transmission of two passive bits after arbitration loss on a byte boundary can be enabled data link operation features 11 bytes transmit buffer double-buffered 11 bytes receive buffer support of in-frame response (ifr) types 1, 2, 3 automatic ifr transmission for ifr types 1, 2 for three byte consolidated headers advanced interrupt handling for rx, tx and error conditions all interrupt sources can be separately enabled/disabled 8-byte transmit fifo and 16-byte receive fifo in block mode
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-2 v2.2, 2004-01 sdlm_x, v2.0 22.2 sdlm kernel description figure 22-1 general block diagram of the sdlm interface the sdlm module communicates with the external world (j1850 bus) via two i/o lines, the receive line rxj1850 (data input signal) and the transmit line txj1850 (data output signal). the module provides the feature to select one out of four possible input pins and one out of four possible output pins. the desired input pin is defined by bitfield is (input selection), the output pin is selected by the altsel bitfield of the port. 22.2.1 j1850 concept the sae class-b specification establishes the requirements for a serial bus protocol used in automotive and industrial applications. basically it describes the network ? s characteristics in three layers: the physical layer, the data link layer and the application layer. the physical layer handles the frame transfer including bit/symbol encoding and timing. the data link layer defines the j1850 protocol in terms of frame elements, error detection, bus access, frame arbitration, and clock synchronization. finally, the application layer needs to evaluate message screening/filtering by software and the handling of diagnostic parameters/codes. the j1850 is a multi-master based serial protocol. each node has a local clock, which allows for simultaneous access to the bus. sdlm module interrupt control output control address decoder (kernel) f sdlm receive transmit rxj1850 txj1850 input control interrupts sdlm_i0 sdlm_i1
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-3 v2.2, 2004-01 sdlm_x, v2.0 22.2.1.1 frame format basics this chapter summarizes the basic definitions of the sae standard class b data communication network interface protocol. the general j1850 frame format is defined as: idle, sof, data_0, ? , data_n, crc, eod, nb, ifr_1, ? , ifr_n, eof, ifs, idle figure 22-2 standard frame types table 22-1 summarizes the used abbreviations. sof header type 0 : no ifr data field type 1 : single byte from a single responder type 2 : single byte from multiple responders type 3 : multiple bytes from a single responder crc sof header data field crc eod nb id sof header data field crc eod id 1 ifs ifs ........... id n ifs sof header data field crc eod ifr data field crc ifs (when nb is active long) nb nb eod eof eod eof eod eof eod eof
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-4 v2.2, 2004-01 sdlm_x, v2.0 table 22-1 abbreviations used symbol name description sof start of frame the sof mark is used to uniquely identify the start of a frame. sof is not used for crc error calculation. data_0 - data_n data bytes data bytes (8 bits); starting with msb first; maximum frame length including header byte(s) and ifr byte(s) but excluding frame delimiters (sof, eod, eof, and ifs) and crc byte is 11 bytes. crc crc byte cyclic redundancy check byte; generated at the transmission and checked during reception. eod end of data indicates the end of a transmission by the originator of a frame; directly after eod an ifr can be started by the recipient(s) of the frame. nb normalization bit required for 10.4 kbps mode only; follows after an eod and before an ifs symbol; defines the start of an in-frame response. ifr_1 - ifr_n in-frame response byte(s) in frame response byte(s) (id) can be sent by receiving devices after the sending device has sent an eod. eof end of frame this symbol defines the end of a frame. ifs inter-frame separation this symbol separates two consecutive frames. idle idle the bus is idle if no transmission takes place.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-5 v2.2, 2004-01 sdlm_x, v2.0 22.2.1.2 j1850 bits and symbols figure 22-3 j1850 variable pulse width (vpw) format table 22-2 timing examples for vpw format frequency tv1 tv2 tv3 tv4 tv5 tv6 10.4 kbit/s 64 s 128 s 200 s 280 s ?? passive active data bit `1' or passive active data bit `0' or start of frame tv2 tv1 tv1 tv2 (sof) tv3 passive active end of frame (eof) tv4 passive active tv3 end of data (eod) passive active normalization bit tv3 passive active eod end of last data bit tv1 or tv2 norm. bit start of ifr bit tv3 passive active eod end of last data bit idle bus, may initiate transmission at any time inter-frame separation tv4 tv6 eof ifs may transmit if rising edge has been detected after an eof > tv3 end of last data bit tv6 eof ifs tv4 break signal passive active
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-6 v2.2, 2004-01 sdlm_x, v2.0 22.2.1.3 frame arbitration the frame arbitration in the j1850 compatible networks follows the concept of carrier sense multiple access (csma) with non-destructive message arbitration. when two nodes have access to the bus at the same time, the priority decision is made during transmission. the node which has won the arbitration will continue transmission and the other node will stop transmitting. the sdlm always receives the current message on the bus in its receive buffer structure, even while transmitting. figure 22-4 j1850 vpw message arbitration 22.2.2 block diagram the sdlm module is built up by two basic blocks, the protocol controller and the data link controller. the protocol controller basically contains the bit stream processor and the two shift registers for the transmit and the receive path. the bit stream processor encodes/decodes the variable pulse width (vpw) data stream and translates incoming vpw symbols into data logic levels. the protocol controller further has 8-bit wide data interfaces to the data link controller. the data link controller can handles incoming and outgoing data using three 8-bit wide data buffers, the 11-byte transmit buffer and two 11-byte receive buffers. further, several control tasks (interrupt, timing, and buffer control) are managed by the data link controller. 0 passive active transmit line of node 1 transmit line of node 2 sof 0 1 1 passive active 00 10 0 00 10 0 sof bit 1 bit 2 bit 3 bit 4 bit 5 passive active j1850 bus
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-7 v2.2, 2004-01 sdlm_x, v2.0 figure 22-5 sdlm kernel block diagram the general configuration of the data link controller is done via the global control register, the clock divider register and the transceiver delay register. the bits within these registers provide the following functions: sdlm enable/disable 4x mode enable/disable block mode enable/disable header type configuration (single or consolidated) normalization bit polarity selection receive buffer overwrite control clock divider for j1850 bus rate to adapt to the peripheral clock frequency compensation of transceiver delay by sdlm transmission of two passive bits after arbitration loss on a byte boundary can be enabled rxj1850 txj1850 int date link controller transmit buffer (11 bytes) receive buffer 0 (11 bytes) receive buffer 1 (11 bytes) data link control 8 8 8 interrupt control timing control control / status bit stream processor digital filter receive shift register transmit shift register crc check / generation protocol controller 8 8 internal fpi bus interface
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-8 v2.2, 2004-01 sdlm_x, v2.0 22.2.2.1 4x mode if high speed mode is used, all j1850 nodes should be configured to 4x mode when supported. those nodes which do not support 4x mode need to tolerate high speed operation (no error sign). enable bit en4x. a break symbol occurrence will generate an interrupt. after break occurrence cpu needs to reset rx/tx status flags. the transceiver delay should not exceed 4 s. 22.2.2.2 break operation break allows bus communication to be terminated. all nodes are reset to a ? reset-to-receive ? state (reset status bits by cpu). after break symbol transition an ifs has to follow for re-synchronization purpose. if a break is sent, the current frame is ignored (if any). a break transmission can be generated setting bit sbrk. a break reception is indicated by bit brk being set. note: after a hardware reset operation the sdlm module is disabled.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-9 v2.2, 2004-01 sdlm_x, v2.0 22.2.3 interrupt handling the sdlm module can generate the interrupts on the following events: protocol related interrupt conditions (combined to interrupt sdlm_i0): ? end of frame detected ? break received ? arbitration lost ? crc error detected ? error detected data receive/transmit interrupt conditions (combined to interrupt sdlm_i1): ? message transmitted ? message received ? header received figure 22-6 interrupt structure of sdlm shorth 1 bus shorted high shortl bus shorted low col collision detected format format error crcer crc error arl arbitration lost break break received endf end of frame header header received msgrec message received msgtra message transmitted errie crcie sdlm_i0 interrupt request flags arlie brkie endfie hdie recie traie 1 reset by errst arlrst brkrst busrst rxrst txrst sdlm_i1 1
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-10 v2.2, 2004-01 sdlm_x, v2.0 22.2.3.1 message operating mode basically two receive buffers (11 byte each) and one 11 byte transmit buffer are available for data transfer. this allows the transfer of a complete j1850 frame without reloading data bytes. the access to the data is handled in fifo mode (read/write to one address) in addition to random mode (read/write to selected bytes at consecutive addresses). in case of a loss of arbitration, an automatic retransmission is started, until the transmit request bit (txrq) is reset by the cpu. for correct transmission, the transmit buffer has to contain valid data (txcpu > 0) when txrq is set. 22.2.3.2 receive operation the receive buffer structure contains two independent 11 byte receive buffers. one of them is located on cpu side and can be directly accessed by the cpu (data and pointers). if this buffer is full (not yet completely read out), it can not be accessed by the j1850 module. data reception over the bus is always done via the receive buffer on bus side. in order to release the receive buffer on cpu side, bit done has to be set. after complete reception of a frame, the buffer on j1850 side is declared full. if both buffers are full, the buffer on j1850 side can be overwritten by a new incoming frame, depending on the user-programmable overwrite enable bit (ovwr). if the cpu buffer is empty and the j1850 buffer is full, both buffers are swapped. by this action, the full buffer can be accessed by the cpu and the empty one is available on j1850 side. the total number of received bytes in the corresponding buffer is indicated by bitfield rxcnt. bitfield rxcpu indicates how many bytes have already been read out. in fifo mode (rxince = 1), cpu data read actions take place via register rxd00 and rxcpu is automatically incremented by 1 after each read action. in random mode (rxince = 0), the buffer bytes can be directly accessed via their address. in this case, rxcpu is not incremented. in order to release a buffer for new message reception, the done bit has to be set. a receive interrupt is generated after complete reception of the whole frame (msgrec = 1). register buffcon provides flags controlling the receive buffer: receive buffer increment enable (rxince): this bit enables fifo mode in addition to random mode: in random mode the cpu has access to each receive buffer byte via its address. in fifo mode, the rxcpu pointer is incremented upon cpu read access until rxcpu == rxcnt (max. 11). this mode allows an easy cpu read transfer from the receive buffer only by addressing rxd00. register buffstat contains information about the receive buffer: rbc, rbb indicate valid data in the receive buffers msglst indicates a lost frame due to a full receive buffer receive in progress (rip) indicates if any receive action is pending break symbol reception is indicated by break received bit (break)
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-11 v2.2, 2004-01 sdlm_x, v2.0 register transstat contains information about the receive operation: header: single byte or consolidated header is received (set after 1 or 3 received bytes) msgrec: indicates a complete frame reception 22.2.3.3 transmit operation data transmission is started by setting the transmission request bit txrq. transmission is aborted by resetting bit txrq by software. fifo mode and random mode are working in the same way as it is described for data reception. a transmit interrupt can be generated after successful transmission of the complete frame (flag msgtra). figure 22-7 transmit operation register buffcon provides flags controlling the transmit buffer: txince enables (analog to rxince) fifo mode for the transmit buffer txrq initiates a frame transmission to the j1850 bus. in case of a lost arbitration, the module automatically retries transmission until the frame has been correctly sent out or the transmit request has been reset by software cpu can initiate a break transmission by setting sbrk register transstat contains information about transmit operations: cpu is informed when a message is currently transmitted (transmission in progress - tip) msgtra indicates a successful frame transmission arl: indicates that arbitration has been lost txbuffer txcnt=0 txcpu=0 txbuffer empty txbuffer txcpu=6 tx buffer is filled by cpu txcnt=0 txbuffer txcnt=0 txcpu=0 txdata succesfully transmitted via j1850 time 10 9 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-12 v2.2, 2004-01 sdlm_x, v2.0 22.2.4 in-frame response (ifr) operation the module supports automatic ifr transmission for type 1, 2 ifr for three-byte consolidated headers (no cpu load required). if the ifrs are handled via the transmit buffer, txcpu indicates the number of bytes to be transmitted. if automatic ifr transmission function is not possible (single byte or one byte consolidated headers): if bit ifren is not set, type 1 and 2 are handled via the transmit buffer, too. if ifren is set, the value stored in ifrval will be transmitted if bit txirf is set. in case of automatic ifr transmission, register ifrval delivers the source id. the value has to be written by the cpu first. ifr type 3 transmission can only be handled by the transmit buffer. setting bit txifr initiates an ifr transmission (if automatic ifr not possible). normalization symbol can be configured by the nb configuration bit. if ifr with crc (type 3, crcen = 1) is used, bit crcerr indicates crc error conditions. if register ifrval is used for transmission, no crc will be sent out (not depending on crcen). if the transmit buffer is used, crc will be sent out if bit crcen is set. bit header indicates complete reception of header byte(s) in the receive buffer on bus side. transmission of type 1 and type 2 ifrs for single byte headers and one byte consolidated headers is also accomplished by bit txifr, which has to be set by software. in case of automatic ifr (for type 1, 2 for three byte consolidated headers and irfen = 1), bit txifr is not needed. 3-byte consolidated headers: if ifren is set, automatic response to type 1 and type 2 ifrs via the ifrval register is enabled. type 3 ifr is sent by writing the ifr to the transmit buffer and then setting bit txifr. if ifren is not set, all ifrs are transmitted via the transmit buffer if txifr is set. single byte headers and one byte consolidated headers: as there is no information in the header to indicate if an ifr is required, automatic transmission of type 1 and 2 ifrs is not possible. if ifrs are used in the system, the header interrupt should be enabled in order to give time to decode the header through software to determine if an ifr is required. ifr transmission is always initiated by setting bit txifr. type 3 ifr is always done via the transmit buffer, whereas types 1, 2 are handled either via the transmit buffer (ifren = 0) or register ifrval (ifren = 1).
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-13 v2.2, 2004-01 sdlm_x, v2.0 22.2.5 block mode in block mode, the sdlm supports transfer of frames of unlimited length (application specific). block mode is selected by bmen = 1. in this case, only one receive buffer and the transmit buffer are available. the swap functionality between the two rxbuffers is no longer supported. in block mode, the receive and the transmit buffers are built as circular buffers of eight bytes length (transmit buffer) and 16 bytes length (receive buffer, see figures below). access in random mode not being useful (but still supported), fifo mode is automatically enabled (not depending on rxince/txince). during transmission, a transmit interrupt can be generated each time txcpu == txcnt is detected after transmission of a byte. during reception, a receive interrupt can be generated if rxcnt0 != rxcpu0 after reception of a byte. the counting sequence for the transmit buffer is ? 6, 7, 0, 1, 2, ? representing a circular buffer of 8 bytes length. the counting sequence for the receive buffer is ? 14, 15, 0, 1, 2, ? representing a circular buffer of 16 bytes length. figure 22-8 transmit in block mode note: the sw has to take care that the condition txcpu == txcnt after writing a byte to the transmit buffer in block mode does not become true, otherwise the transmission will be finished. 7 65 4 3 2 1 0 7 65 4 3 2 1 0 7 65 4 3 2 1 0 7 65 4 3 2 1 0 7 65 4 3 2 1 0 txcpu=0 txcnt=0 buffer before cpu loading tx circular buffer txcnt=0 cpu load txbuffer t xcp u = 3 block mode transmission byte 4 currently transmitted interrupt is generated when txcnt=txcpu tx initiated by setting txrq t x cnt=5 cpu continues loading txbuffer t xc p u=3 txcnt =3 end of block mode transmission msgtra time time txcpu=0 txcnt=0 buffer after block mode transmission t xcpu=5 7 65 4 3 2 1 0 tx cnt=5 txcpu=5
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-14 v2.2, 2004-01 sdlm_x, v2.0 in order to monitor the status of the bus during transmission, the sdlm always reads on the bus, even while transmitting. as a result, the user can check whether the message sent is equal to the message on the bus (test for arbitration). the receive buffer in block mode can be accessed via register rxd00 on cpu side as fifo base address (relative address 40 h ). the elements of the fifo can always be accessed via their addresses, too. the first eight bytes are located at the relative addresses 40 h to 47 h , the second eight bytes at the relative addresses 50 h to 57 h . figure 22-9 data reception in block mode in block mode, the interrupt request flags msgrec (reception) and msgtra (transmission) are automatically reset by hardware upon a read action from rxd00, or a write action to txd0 respectively. rbb (= rbc) is set upon a pointer match after reception of a byte (receive buffer full) and reset by a read action from this buffer. msglst is set if rbb has been set before and a new data byte is received. msglst is not automatically reset by hardware. all error flags remain pending (once set) and have to be cleared by software. in case of a detected error during transmission, the transmit request bit txrq is reset by hardware in order to abort the transmission (no automatic retry). 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 15 ... 4 3 2 1 0 rxcpu=0 rxcnt=0 rxbuffer before block data reception rx circular buffer rxcnt=0 16 bytes received, rxbuffer full rxcnt=5 block mode receive finished msgrec time time rxcpu=0 r x cn t =1 rxcpu=0 interrupt generation after reception of each byte r xc p u = 5 ... ... ... 15 15 15 ... ... ... ...
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-15 v2.2, 2004-01 sdlm_x, v2.0 22.2.6 bus access in fifo mode in fifo mode (block mode or normal mode), the fifos are byte-oriented. in order to avoid mismatch in case of word accesses, the lsb of the pointers on cpu side select which byte of the word is taken into account. in the 16-bit implementation, the lsb of the cpu pointer (rxcpu or txcpu, respectively) determines which byte is taken into account. the receive fifo only delivers one data byte (its position in the word is selected by the lsb), the other byte is 0. the pointer is incremented by one after each read access to rxd00. the transmit buffer only takes over one byte per write access to txd0, according to the lsb of the pointer. the other byte is not changed. if the pointer ? s lsb is 0, any access to the corresponding buffer is based on the low byte (read: higher bytes = 0, low byte = fifo value, write: only low byte written). if the pointer ? s lsb is 1, any access to the corresponding buffer is based on the high byte (read: high byte = fifo value, lowbyte = 0, write: only high byte written). in any case, the pointer is incremented by 1. other accesses than to the receive or transmit buffers are always based on the low byte. any word access to the sdlm (if fifo mode is not selected) effects only the low-byte.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-16 v2.2, 2004-01 sdlm_x, v2.0 22.2.7 flowcharts 22.2.7.1 overview figure 22-10 initialization, data setup and transmission in order to adapt the timing to the transceiver device, register txdelay has to be configured, too. furthermore, the desired j1850 receive pin and the transmit pin have to be selected. the interrupt line sdlm_i1 can be combined either with sdlm_i0 or can be independent. globcon:=19h clkdiv:=84h buffcon:=00 load data in txbuffer end configure j1850 loading data into txbuffer data transmission msgtra:=1 (bit 0 transstat) txrq:=0 (bit 1 buffcon) after succesful transmission an interrupt will be generated if the interrupt enable bit traie is set. done by hw txdata0 txdata1 txdata2 txdata3 txdata4 txdata5 txdata6 txdata7 txdata8 txdata9 txdata10 txbuffer transmit data j1850 module is enabled clken is enabled divider 5mhz crystal frequency) fifo mode is disabled txcpu will not be incremented, bytes in buffer have to be addressed. start 30h 3ah set txrq
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-17 v2.2, 2004-01 sdlm_x, v2.0 22.2.7.2 transmission control transmission of a standard message in fifo mode bit txince in register buffcon has to be set in order to provide fifo functionality. bitfield txcpu is incremented after each write operation to txd0. the transmit buffer is filled by multiple write actions to txd0. all other registers of the transmit buffer can always be directly accessed via their addresses without changing txcpu. figure 22-11 transmission in fifo mode start tip=1 ? txrq:=0 more bytes ? write byte to txd0 txcpu >0 ? arlrst:=1 txrst:=1 txrq:=1 end y n y n y n the transmit buffer should not be modified while the module is transmitting. the transmission request (if there is still one pending) for the current transmit buffer is cleared. data bytes (max. 11) are written to the fifo base address. in fifo mode, txcpu is automatically incremented after each write to txd0. the transmit buffer has to be filled (at least one byte) to be valid for transmission. the transmission related status flags are cleared to get defined starting conditions. other flags can be cleared optionally. the transmit buffer is declared valid (transmission is requested). txrq is automatically reset after succesful transmission (an interrupt can be generated, see bit msgtra).
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-18 v2.2, 2004-01 sdlm_x, v2.0 transmission of a standard message in random mode figure 22-12 transmission in random mode start tip=1 ? txrq:=0 more bytes ? write byte to dedicated address txdn arlrst:=1 txrst:=1 txrq:=1 end y n y n the transmit buffer should not be modified while the module is transmitting. the transmission request (if there is still one pending) for the current transmit buffer is cleared. data bytes (max. 11) have to be written to the dedicated addresses inside the transmit buffer. in normal mode, txcpu is not incremented. the register txcpu has to be set by sw to the number of bytes which shall be transmitted (1 to 11) to be valid for transmission. the transmission related status flags are cleared to get defined starting conditions. other flags can be cleared optionally. the transmit buffer is declared valid (transmission is requested). txrq is automatically reset after succesful transmission (an interrupt can be generated, see bit msgtra). txcpu:=n
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-19 v2.2, 2004-01 sdlm_x, v2.0 transmission in block mode block mode is selected by bmen = 1 in register globcon. in block mode, fifo access is automatically enabled (not dependent on rxince or txince). the transmit buffer in block mode is 8 bytes long. figure 22-13 transmission in block mode start msgtra=1 ? end y the sw has to check what kind of error has been detected to run an appropriate servive routine. bit msgtra=1 indicates that a complete byte has been sent on the bus, that the transmission of the last byte is in progress and that the module waits for a new byte. if no more bytes are written to txd0, the sdlm will terminate the transmission with an eod symbol. this write action automatically resets bit msgtra. bit break=1 indicates that a break symbol has been received. this terminates the message and optionally block mode, too. n more bytes ? stop transmission brkrst:=1 y n write txd0 break=1 ? error handling y n
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-20 v2.2, 2004-01 sdlm_x, v2.0 22.2.7.3 read operations read of the receive fifo in normal mode bit rxince in register buffcon has to be set in order to provide fifo functionality. register rxcpu is incremented after each read operation from rxd00. the receive buffer is read out by multiple read actions from rxd00. all other registers of the receive buffer can always be directly accessed via their addresses without changing rxcpu. figure 22-14 receive operation in fifo mode start rbc=1 ? read rxd00 end y the cpu releases the receive buffer by setting bit done. this action resets rbc. if the receive buffer on bus side contains valid data (rbb=1 and rbc=0), the buffers are swapped. bit rbc=1 indicates that the receive buffer on bus side contains valid data and has not yet been released by the cpu. the cpu reads from rxd00, which is the base address of the fifo. after each read action, rxcpu is incremented by hw. if rxcpu (number of bytes already read out) is lower than rxcnt (total number of bytes in the receive buffer), the cpu has to continue reading rxd00. n rxcpu XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-21 v2.2, 2004-01 sdlm_x, v2.0 read operation in block mode block mode is selected by bmen = ? 1 ? in register globcon. in block mode, fifo access is automatically enabled (not dependent on rxince or txince). the receive buffer in block mode is 16 bytes long. figure 22-15 reception in block mode the value of the rxcpu pointer is automatically copied to register sptr (start of frame pointer) to allow the user to detect the begin of a new frame. start msgrec=1 ? bytecount:=0 busrst:=1 end y the sw has to check what kind of error has been detected to run an appropriate servive routine. bit msgrec=1 indicates that a new byte has been received, which can be read via rxd00. this read action automatically resets bit msgrec. an optional sw byte counter can be incremented to detect the frame length. bit break=1 indicates that a break symbol has been received. this terminates the message and optionally block mode, too. bit endf=1 indicates that the frame is finished. the byte counter has to be reset to get defined starting conditions for the next frame. bit done can be set optionally to clear the pointers. n endf=1 ? bytecount:=0 brkrst:=1 opt.: abort bm y n read rxd00 bytecount++ break=1 ? error handling n y
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-22 v2.2, 2004-01 sdlm_x, v2.0 22.2.8 ifr handling 22.2.8.1 ifr types 1, 2 via ifrval the header bit is automatically set by hardware after reception of the complete header (1 or 3 bytes) in the receive buffer on bus side. this buffer can be accessed at the consecutive relative addresses starting at base + 50 h . in case of 3-byte consolidated headers with the k bit set, an ifr (via ifrval) will be automatically generated if bit ifren is set. the header bit is reset when rxrst is set by software or after the reception of the complete frame. in case of single-byte headers or one-byte consolidated headers, the flowchart shows a possibility to send ifr. if an ifr is requested (automatically or by hardware), the ifr byte(s) are sent after the eod symbol. in case of type 2 ifr, automatic retry after arbitration loss takes place depending on bit arifr. figure 22-16 ifr handling via ifrval start header=1 analysis of received header bytes ifr needed ? txifr:=1 end y the currently received frame (on bus side) is accessable in random mode at consecutive addresses starting at base+ 50h. the user has to decide by sw whether an ifr of one byte is required or not. the transmission of the ifr is requested by setting bit txifr. bit ifren has to be set in order to send an ifr with the content of ifrval (without crc). if the ifr byte does not change, ifrval has to be written only once during initialisation. load ifrval n
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-23 v2.2, 2004-01 sdlm_x, v2.0 22.3 sdlm register description figure 22-17 sdlm register overview system registers globel kernel control registers data buffer control registers pisel globcon txcnt ic0 clkdiv txcpu ic1 txdelay rxcnt ifr rxcpu buffstat rxcntb transstat sofptr busstat errstat buffcon flagrst intcon transmit buffer registers receive buffer 0 (on cpu side) registers receive buffer 1 (on bus side) registers txd0 rxd00 rxd10 txd2 rxd02 rxd12 txd4 rxd04 rxd14 txd6 rxd06 rxd16 txd8 rxd08 rxd18 txd10 rxd010 rxd110
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-24 v2.2, 2004-01 sdlm_x, v2.0 22.3.1 global control and timing registers the global control register contains bits to select different transfer modes and to determine the message handling. globcon global control register reset value: 0000 h 1514131211109876543210 0 pb sel ar ifr ov wr nb hdt bm en en 4x gm en r rwrwrwrwrwrwrwrw field bits type description gmen 0rw global module enable 0 the complete sdlm module is disabled. 1 the sdlm module is enabled and data transmission via the serial bus is possible. resetting gmen by software from ? 1 ? to ? 0 ? resets the module, except the timings. en4x 1) 1rw high speed transfer enable (4x) 0 the data transfer rate is 10.4 kbit/s. 1 the data transfer rate is 41.6 kbit/s. bmen 2rw block mode enable 0 the maximum frame length is 11 data bytes (normal mode). 1 transfers of frames longer than 11 data bytes are enabled. the transmit and the receive buffers are organized as circular buffers, which can be accessed in fifo mode. resetting bmen resets the buffer pointers. hdt 3rw header type 0 single byte headers are supported. 1 consolidated headers (1 byte and 3 bytes) are supported. nb 4rw normalization bit polarity 0 normalization bit is functional 0. 1 normalization bit is functional 1.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-25 v2.2, 2004-01 sdlm_x, v2.0 ovwr 5rw overwrite enable 0 overwrite action of the receive buffer on sdlm side in case of an incoming frame and a full receive buffer on bus side (rbb = 1) disabled. the frame on the bus is not accepted and is lost. 1 the full buffer on bus side is declared empty and then overwritten by the next incoming frame. the frame in the receive buffer on bus side is lost. arifr 6rw automatic retry of ifr 0 the module will not retry transmission of ifr byte(s) in case of an arbitration loss (handling of ifr types 1, 3). the collision detection mechanism is generally enabled during ifr. 1 an automatic retry of ifr transmission in case of arbitration loss is enabled (for ifr type 2). the collision detection mechanism is disabled during eod. pbsel 7rw passive bits select 0 when loosing arbitration during the last bit of a byte (on a byte boundary) during the normal frame, two passive bits are automatically transmitted by the module. the passive bits are never added during ifr. 1 no extra action after the loss of arbitration (the two passive bits are not added). 0 [15:8] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? . 1) in order to support transmission in 4x mode, the transceiver delay should not exceed 4 s. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-26 v2.2, 2004-01 sdlm_x, v2.0 register clkdiv allows for configuration of the internal timings. clkdiv clock divider register reset value: 0000 h 1514131211109876543210 0 clk en clk sel cd rrwrwrw field bits type description cd [5:0] rw clock divider bits this bitfield defines the value of the clock divider. in order to run the module with different system frequencies, the divider can be programmed from 1 to 64. 000000 b system clock/module clock = 1 000001 b system clock/module clock = 2 000010 b system clock/module clock = 3 000011 b system clock/module clock = 4 ? 111110 b system clock/module clock = 63 111111 b system clock/module clock = 64 clksel 6rw clock select 0 1.00 mhz module clock 1 1.05 mhz module clock clken 1) 1) only registers globcon, clkdiv and ipcr can be accessed if clken = 0. 7rw clock enable 0 module clock is gated off (protocol layer not clocked) in order to reduce power consumption. 1 module is clocked, protocol layer working. 0 [15:8] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-27 v2.2, 2004-01 sdlm_x, v2.0 register txdelay allows for the compensation of the transceiver delay. txdelay transceiver delay register reset value: 0014 h 1514131211109876543210 0rinvtd rrwrw field bits type description td [5:0] rw transceiver delay bits this bitfield defines the transceiver delay, which is taken into account by the j1850 bitstream processor. the value of td determines the number of module clock cycles, which are taken into account. the reset value equals 20 s @ 1.00 mhz or 19 s @ 1.05 mhz. rinv 6rw invert receive input 0 receive pin polarity is not inverted. 1 receive pin polarity is inverted. 0 [15:7] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-28 v2.2, 2004-01 sdlm_x, v2.0 register ifr contains the ifrval bitfield, which can be sent out as source id in case of an one-byte ifr (automatic transmission or triggered by sw). ifr in-frame response value register reset value: 0000 h 1514131211109876543210 0ifrval rrw field bits type description ifrval [7:0] rw in-frame response value bitfield ifrval contains the value to be transmitted in case of requested in-frame response (type 1, 2 ifr, 1 byte response). has to be enabled by bit ifren and initialized by the cpu. 0 [15:8] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-29 v2.2, 2004-01 sdlm_x, v2.0 22.4 control and status registers register buffstat contains the buffer-related status flags. buffstat buffer status register reset value: 0000 h 1514131211109876543210 0 rbc rbb msg lst rip tip r rhrhrhrhrh field bits type description tip 0rh transmission in progress 0 the sdlm module does not currently send a frame on the bus or has finished its transmission. 1 the sdlm module is sending the contents of its transmit buffer or ifr.ifrval on the bus and has not yet lost arbitration. tip is reset by hardware when the arbitration is lost or eod or endf are detected. rip 1rh reception in progress 0 the sdlm module does not currently receive a frame on the bus. 1 the sdlm module is receiving a frame on the bus. rip is reset by hardware when endf is detected. msglst 2rh message lost bit msglst indicates an incoming frame when the receive buffer on bus side is full (rbb = 1, contains received message data and has not yet been swapped). bit msglst is reset when msgrec is reset in normal mode. if overwrite is enabled, the receive buffer on bus side will be overwritten. in block mode, msglst is set if rbb is set and a new byte is received. if ovwr = 0, the new byte is not stored. if ovwr = 1, the new byte is stored. msglst has to be reset by software.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-30 v2.2, 2004-01 sdlm_x, v2.0 rbb 3rh receive buffer on bus side full rbb = ? 1 ? indicates that the receive buffer on j1850 side is full. in case of a new incoming message, this buffer is declared empty (rbb = 0) and overwritten by the new data if bit ovwr = ? 1 ? . if bit ovwr = 0, the buffer status and its contents are not changed (new data is not received). rbb is reset by hardware when the buffer is swapped to cpu side. in block mode, (only one buffer, so rbb = rbc) rbb is set upon a pointer match after reception of a byte. it is reset by reading from the receive buffer. rbc 4rh receive buffer on cpu side full rbc = ? 1 ? indicates that the receive buffer on cpu side is full (not empty). this buffer remains allocated by the cpu and bit rbc remains set until bit done has been set by software. 0 [15:5] ? reserved; returns ? 0 ? if read. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-31 v2.2, 2004-01 sdlm_x, v2.0 register transstat contains transmission-related status flags and monitors three functional bits of the header of the currently received frame. transstat transmission status register reset value: 0000 h 1514131211109876543210 0 y k h arl br eak hea der msg rec msg tra r rhrhrhrhrhrhrhrh field bits type description msgtra 0rh message transmitted normal mode: msgtra indicates the complete transmission of the txbuffer or ifrval (arbitration won and eod detected). reset by bit txrst. block mode: msgtra is set upon a pointer match after transmission of a byte or endf detection. it is reset when the cpu writes to the transmit buffer or by bit txrst. msgrec 1rh message received normal mode: msgrec indicates the reception of a new frame in the receive buffer on bus side (detection of endf). it is reset by bit rxrst or by hardware if the buffer is overwritten. block mode: msgrec is set if the pointers do not match after reception of a byte (fifo not empty) or endf detection. it is reset when the cpu reads from the receive buffer or by bit rxrst. header 2rh header received header is set by hardware after reception of the complete header byte(s). it is reset by hardware after reception of the complete frame. break 3rh break received if break is set, a break symbol has been received on the j1850 bus. has to be reset by software.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-32 v2.2, 2004-01 sdlm_x, v2.0 arl 4rh arbitration lost arl is set after the arbitration for transmission has been lost. it is reset by software or by hardware if the arbitration has been won or the transmission has been aborted. h 5rh h bit in consolidated headers this bit monitors the status of bit 4 of the first byte in a frame on bus side. k 6rh k bit in 3 byte consolidated headers this bit monitors the status of bit 3 of the first byte in a frame on bus side. y 7rh y bit in 3 byte consolidated headers this bit monitors the status of bit 2 of the first byte in a frame on bus side. 0 [15:8] ? reserved; returns ? 0 ? if read. field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-33 v2.2, 2004-01 sdlm_x, v2.0 register busstat contains bus-related status bits. busstat bus status register reset value: 0000 h 1514131211109876543210 0idle end f eod sof r rhrhrhrh field bits type description sof 0rh start of frame detected indicates the detection of sof; bit is reset by busrst. eod 1rh end of data detected indicates the detection of eod; bit is reset by busrst. endf 2rh end of frame detected indicates the detection of eof; bit is reset by busrst idle 3rh bus idle this bit is set after ifs. it is reset by hw if a new frame has started. 0 [15:4] ? reserved; returns ? 0 ? if read.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-34 v2.2, 2004-01 sdlm_x, v2.0 register errstat contains error bits. the bits in this register have to be reset by sw. errstat error status register reset value: 0000 h 1514131211109876543210 0 cr cer col sho rth sho rtl for mat r rhrhrhrhrh field bits type description format 0rh format error bit is set if a frame length error, byte length error, symbol timing error or bit timing error occurred. shortl 1rh bus shorted low this bit is set if the device tries to sent data, but permanently reads a ? 0 ? on the bus. shorth 2rh bus shorted high this bit is set if a ? 1 ? is detected on the bus for more than one second. col 3rh collision detected this bit is set if a collision has been detected on the bus. crcer 4rh crc error this bit is set if the calculated crc differs from the received one. 0 [15:5] ? reserved; returns ? 0 ? if read.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-35 v2.2, 2004-01 sdlm_x, v2.0 register buffcon contains the transfer-related control bits, including ifr control and fifo control. buffcon buffer control register reset value: 0000 h 1514131211109876543210 0 rx ince tx ince ifr en crc en s brk do ne tx rq tx ifr r rwrwrwrwrwhrwhrwhrwh field bits type description txifr 0rwh transmit in-frame response setting bit txifr declares the transmit buffer or the ifr register (if ifren = 1, ifr type 1, 2, others than 3 byte consolidated header) to be valid for ifr and initiates its transmission. txifr is automatically reset by hardware after successful transmission. resetting txifr by software stops the transmission of the ifr. txrq 1rwh transmit request setting bit txrq declares the transmit buffer to be valid and starts its transmission. txrq is automatically reset by hardware after successful transmission. resetting txrq by software stops the transmission in normal mode and in block mode. txrq can not be used to start ifr transmission from the transmit buffer. if txrq is reset, txcpu is cleared. done 2rwh receive buffer on cpu side read out done setting bit done declares the receive buffer on cpu side to be empty, resets rxcpu and releases the buffer (reset of rbc). if there is a full receive buffer on bus side, the buffers are swapped. this bit is reset by hardware after the buffer has been released. sbrk 3rwh send break setting bit sbrk initiates the transmission of a break symbol on the j1850 bus. bit sbrk is reset by hardware after having sent the break symbol.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-36 v2.2, 2004-01 sdlm_x, v2.0 crcen 4rw crc enable 0 no crc generation for type ifr via txbuffer 1 crc enabled for ifr via txbuffer if ifr is sent from ifrval, no crc is generated (even if crcen = 1). crc generation is always enabled in normal mode and in block mode. ifren 5rw in-frame response enable setting bit ifren enables the automatic ifr (type1, 2 for 3 byte consolidated header) of the sdlm module with the value stored in ifrval. if the ifr request can not be automatically detected (all headers, except see above), ifren selects the data source for types 1, 2 ifr initiated by txifr. 0 transmit buffer contains ifr data byte(s), ifr types 1, 2, 3 supported, crc depending on crcen. 1 ifrval contains data byte for types 1, 2 ifr. automatic ifr for types 1, 2 for 3 byte consolidated headers supported. no crc is used. txince 6rw transmit buffer increment enable random access mode is always enabled. 0 fifo mode disabled for transmit buffer. 1 fifo mode enabled, txcpu is incremented by one after each cpu write operation to the txd0. in block mode, fifo mode is automatically enabled (not depending on txince). rxince 7rw receive buffer increment enable random access mode is always enabled. 0 fifo mode disabled to receive buffer on cpu side. 1 fifo mode enabled, rxcpu is incremented by one after each cpu read operation to rxd00. in block mode, fifo mode is automatically enabled (not depending on rxince). 0 [15:8] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? . field bits type description
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-37 v2.2, 2004-01 sdlm_x, v2.0 register flagrst contains the control bits to reset the error flags, the bus-related flags and the transfer-related status bits. flagrst flag reset register reset value: 0000 h 1514131211109876543210 0 er rst bus rst rx rst tx rst arl rst brk rst r whwhwhwhwhwh field bits type description brkrst 1) 1) this bit is automatically reset by hw after clearing bit break and delivers ? 0 ? when read. 0wh reset buffer status flag resets break arlrst 2) 2) this bit is automatically reset by hw after clearing bit arl and delivers ? 0 ? when read. 1wh reset buffer status flag resets arl txrst 3) 3) this bit is automatically reset by hw after clearing bit msgtra and delivers ? 0 ? when read. 2wh reset buffer status flag resets msgtra rxrst 4) 4) this bit is automatically reset by hw after clearing bits msgrec and msglst and delivers ? 0 ? when read. 3wh reset buffer status flag resets msgrec and msglst busrst 5) 5) this bit is automatically reset by hw after clearing bits endf, eod and sof and delivers ? 0 ? when read. 4wh reset bus status flags resets endf, eod, sof errst 6) 6) this bit is automatically reset by hw after clearing bits shorth, shortl, col, crcer and format and delivers ? 0 ? when read. 5wh reset error flags resets shorth, shortl, col, crcer, format 0 [15:6] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-38 v2.2, 2004-01 sdlm_x, v2.0 register intcon contains all interrupt enable bits. intcon interrupt control register reset value: 0000 h 1514131211109876543210 0 err ie crc ie arl ie brk ie end f ie hd ie rec ie tra ie r rwrwrwrwrwrwrwrw field bits type description traie 0rw enable transmit interrupt the transmission interrupt is disabled. an interrupt is generated if bit msgtra is set. recie 1rw enable receive interrupt the receive interrupt is disabled. an interrupt is generated if bit msgrec is set. hdie 2rw enable header received interrupt the header interrupt is disabled. an interrupt is generated if bit header is set. endfie 3rw enable end of frame detection the end-of-frame interrupt is disabled. an interrupt is generated if bit endf is set. brkie 4rw enable break received interrupt the break interrupt is disabled. an interrupt is generated if bit break is set. arlie 5rw enable arbitration lost interrupt the arbitration-lost interrupt is disabled. an interrupt is generated if bit arl is set. crcie 6rw enable crc error interrupt the crc error interrupt is disabled. an interrupt is generated if bit crcer is set. errie 7rw enable error interrupt the error interrupt is disabled. an interrupt is generated if one of the bits shorth, shortl or format is set. 1) 1) the col flag does not generate an error interrupt! 0 [15:8] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-39 v2.2, 2004-01 sdlm_x, v2.0 22.4.1 transmission related registers register txcnt contains the number of bytes of the transmit buffer, which have already been sent out on the bus. txcnt bus transmit byte counter register reset value: 0000 h 1514131211109876543210 0txcnt rrh field bits type description txcnt [3:0] rh bus transmit byte counter bitfield txcnt contains the number of bytes transmitted by the sdlm module. txcnt is reset by resetting bit txrq. a transmit interrupt can be generated when txrq is reset by hardware. txcpu equal to txcnt and successful transmission (arbitration not lost) resets bit txrq by hardware in normal mode. = pointer for sdlm access to transmit buffer 0 [15:4] ? reserved; returns ? 0 ? if read.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-40 v2.2, 2004-01 sdlm_x, v2.0 register txcpu contains the pointers to the next empty byte in the transmit buffer (= number of bytes in the transmit buffer). txcpu cpu transmit byte counter register reset value: 0000 h 1514131211109876543210 0txcpu rrwh field bits type description txcpu [3:0] rwh cpu transmit byte counter bitfield txcpu contains the number of bytes, which have been written to the transmit buffer by the cpu. in fifo mode (txince = ? 1 ? or bmen = ? 1 ? ), txcpu is incremented by 1 after each cpu write action to register txd0. in random mode only (txince = 0 and bmen = 0), txcpu has to be written by software before setting the transmit request bit (txrq) in order to define the number of bytes to be sent. txcpu is reset by resetting bit txrq in normal mode or resetting bmen. for more details see txcnt = pointer for cpu access to transmit buffer in fifo mode. 0 [15:4] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-41 v2.2, 2004-01 sdlm_x, v2.0 the transmit data registers contain the data bytes in the transmit buffer. in random mode mode, all data bytes can be directly accessed via their addresses, whereas in fifo mode, only txd0 should be used. txd0 transmit data register 0 reset value: 0000 h 1514131211109876543210 txdata1 txdata0 rw rw field bits type description txdata0 [7:0] rw transmit buffer data byte 0 txdata1 [15:8] rw transmit buffer data byte 1 txd2 transmit data register 2 reset value: 0000 h 1514131211109876543210 txdata3 txdata2 rw rw field bits type description txdata2 [7:0] rw transmit buffer data byte 2 txdata3 [15:8] rw transmit buffer data byte 3 txd4 transmit data register 4 reset value: 0000 h 1514131211109876543210 txdata5 txdata4 rw rw field bits type description txdata4 [7:0] rw transmit buffer data byte 4 txdata5 [15:8] rw transmit buffer data byte 5
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-42 v2.2, 2004-01 sdlm_x, v2.0 txd6 transmit data register 6 reset value: 0000 h 1514131211109876543210 txdata7 txdata6 rw rw field bits type description txdata6 [7:0] rw transmit buffer data byte 6 txdata7 [15:8] rw transmit buffer data byte 7 txd8 transmit data register 8 reset value: 0000 h 1514131211109876543210 txdata9 txdata8 rw rw field bits type description txdata8 [7:0] rw transmit buffer data byte 8 txdata9 [15:8] rw transmit buffer data byte 9 txd10 transmit data register 10 reset value: 0000 h 1514131211109876543210 0 txdata10 rrw field bits type description txdata10 [7:0] rw transmit buffer data byte 10 0 [15:8] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-43 v2.2, 2004-01 sdlm_x, v2.0 22.4.2 reception related registers register rxcnt contains the number of bytes received in this buffer. rxcnt bus receive byte counter register (on cpu side) reset value: 0000 h 1514131211109876543210 0rxcnt rrh field bits type description rxcnt [3:0] rh receive byte counter bitfield rxcnt contains the number of received bytes in the receive buffer on cpu side. = pointer for sdlm access to receive buffer rxcnt is reset when the receive buffer on cpu side is released (see done). 0 [15:4] ? reserved; returns ? 0 ? if read.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-44 v2.2, 2004-01 sdlm_x, v2.0 register rxcpu contains the number of bytes already read out from this buffer. rxcpu cpu receive byte counter register (on cpu side) reset value: 0000 h 1514131211109876543210 0rxcpu rrwh field bits type description rxcpu [3:0] rwh cpu receive byte counter bitfield rxcpu contains the number of bytes read out by the cpu. in fifo mode (rxince = ? 1 ? or bmen = ? 1 ? ), rxcpu is incremented by 1 after each cpu read action to register rxd00. in random mode (rxince = 0 and bmen = 0), rxcpu is not used and is 0. = pointer for cpu access to receive buffer rxcpu is reset when the receive buffer on cpu side is released. 0 [15:4] ? reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-45 v2.2, 2004-01 sdlm_x, v2.0 the receive data registers contain the data bytes in the receive buffer. in random mode mode, all data bytes can be directly accessed via their addresses, whereas in fifo mode, only rxd00 should be used. bitfields rxdata0x (x = 0 ? 10) represent the receive buffer 0 on cpu side, bitfields rxdata1x (x = 0 ? 10) represent the receive buffer 1 on bus side. in block mode, the 16-byte receive buffer is built by bitfields rxdata00-07 and bitfields rxdata10-17. rxd00 receive data register 00 (on cpu side) reset value: 0000 h 1514131211109876543210 rxdata01 rxdata00 rh rh field bits type description rxdata00 [7:0] rw receive buffer 0 data byte 0 rxdata01 [15:8] rw receive buffer 0 data byte 1 rxd02 receive data register 02 (on cpu side) reset value: 0000 h 1514131211109876543210 rxdata03 rxdata02 rh rh field bits type description rxdata02 [7:0] rh receive buffer 0 data byte 2 rxdata03 [15:8] rh receive buffer 0 data byte 3
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-46 v2.2, 2004-01 sdlm_x, v2.0 rxd04 receive data register 04 (on cpu side) reset value: 0000 h 1514131211109876543210 rxdata05 rxdata04 rh rh field bits type description rxdata04 [7:0] rh receive buffer 0 data byte 4 rxdata05 [15:8] rh receive buffer 0 data byte 5 rxd06 receive data register 06 (on cpu side) reset value: 0000 h 1514131211109876543210 rxdata07 rxdata06 rh rh field bits type description rxdata06 [7:0] rh receive buffer 0 data byte 6 rxdata07 [15:8] rh receive buffer 0 data byte 7 rxd08 receive data register 08 (on cpu side) reset value: 0000 h 1514131211109876543210 rxdata09 rxdata08 rh rh field bits type description rxdata08 [7:0] rh receive buffer 0 data byte 8 rxdata09 [15:8] rh receive buffer 0 data byte 9
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-47 v2.2, 2004-01 sdlm_x, v2.0 register rxptrb contains the bitfield indicating the number of received bytes in the receive buffer on bus side. rxd010 receive data register 010 (on cpu side) reset value: 0000 h 1514131211109876543210 0 rxdata010 rh rh field bits type description rxdata010 [7:0] rh receive buffer 0 data byte 8 0 [15:8] ? reserved; returns ? 0 ? if read. rxcntb bus receive byte counter register (on bus side) reset value: 0000 h 1514131211109876543210 0 rxcntb rrh field bits type description rxcntb [3:0] rh receive byte counter bitfield rxcntb contains the number of received bytes in the receive buffer on bus side. 0 [15:4] ? reserved; returns ? 0 ? if read.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-48 v2.2, 2004-01 sdlm_x, v2.0 register sofptr contains the bitfield indicating the value of rxcnt after the last endf detection in block mode. receive buffer on bus side: sofptr start-of-frame pointer register reset value: 0000 h 1514131211109876543210 0 sofcnt rrh field bits type description sofcnt [3:0] rh start-of-frame counter for block mode the value of bitfield rxcnt is automatically copied to this bitfield if an end-of-frame symbol is detected. this feature can be used in block mode to determine the position of the first new byte of a frame in 16-byte receive buffer. 0 [15:4] ? reserved; returns ? 0 ? if read. rxd10 receive data register 10 (on bus side) reset value: 0000 h 1514131211109876543210 rxdata11 rxdata10 rh rh field bits type description rxdata10 [7:0] rh receive buffer 1 data byte 0 rxdata11 [15:8] rh receive buffer 1 data byte 1
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-49 v2.2, 2004-01 sdlm_x, v2.0 rxd12 receive data register 12 (on bus side) reset value: 0000 h 1514131211109876543210 rxdata13 rxdata12 rh rh field bits type description rxdata12 [7:0] rh receive buffer 1 data byte 2 rxdata13 [15:8] rh receive buffer 1 data byte 3 rxd14 receive data register 14 (on bus side) reset value: 0000 h 1514131211109876543210 rxdata15 rxdata14 rh rh field bits type description rxdata14 [7:0] rh receive buffer 1 data byte 4 rxdata15 [15:8] rh receive buffer 1 data byte 5 rxd16 receive data register 16 (on bus side) reset value: 0000 h 1514131211109876543210 rxdata17 rxdata16 rh rh field bits type description rxdata16 [7:0] rh receive buffer 1 data byte 6 rxdata17 [15:8] rh receive buffer 1 data byte 7
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-50 v2.2, 2004-01 sdlm_x, v2.0 22.5 sdlm module register table table 23-1 shows all register which are required for programming of the sdlm module. it summarizes the sdlm registers and defines the addresses and reset values. rxd18 receive data register 18 (on bus side) reset value: 0000 h 1514131211109876543210 rxdata19 rxdata18 rh rh field bits type description rxdata18 [7:0] rh receive buffer 1 data byte 8 rxdata19 [15:8] rh receive buffer 1 data byte 9 rxd110 receive data register 110 (on bus side) reset value: 0000 h 1514131211109876543210 0 rxdata110 rh rh field bits type description rxdata110 [7:0] rh receive buffer 1 data byte 10 0 [15:8] ? reserved; returns ? 0 ? if read.
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-51 v2.2, 2004-01 sdlm_x, v2.0 22.6 XC161 module implementation details this section describes: the sdlm module related interfaces such as port connections and interrupt control all sdlm module related registers with its addresses and reset values 22.6.1 interfaces of the sdlm module in XC161 the sdlm module is connected to port pins according to figure 22-18 . figure 22-18 sdlm module io interface the input receive pins can be selected by bitfield ris in the sdlm_pisel register. the output transmit pins are defined by the corresponding altsel registers of port 4, port 7 or port 9. address decoder sdlm module (kernel) f sdlm sdlm_i0 interrupt control txd rxd pisel mux 2 p4.4_rx p4.6_rx p4.7_tx p7.7_rx p9.3_rx p7.6_tx sdlm_i1 note :- sdlm_i1 shares an interrupt node with either sdlm_i0 or can7int. port 4 control p4.4 p4.6 p4.7 altsel port 7 control p7.6 p7.7 altsel port 9 control p9.2 p9.3 altsel p9.2_tx
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-52 v2.2, 2004-01 sdlm_x, v2.0 the sdlm module kernel has two interrupt request lines. the interrupt request line sdlm_i1 can share a interrupt node with sdlm_i0, or alternatively with the twincan interrupt request line 7. the selection is controlled via bitfield i1sel in the sdlm_pisel register. this is illustrated in figure 22-19 . figure 22-19 sdlm interrupt handling i1sel 0 1 sdlm_i0 sdlm_i1 can7int sdlm_ic can7_ic '0' sdlm module sdlm kernel
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-53 v2.2, 2004-01 sdlm_x, v2.0 22.6.2 sdlm module related external registers figure 22-20 shows the module related external registers which are required for programming the sdlm module. figure 22-20 sdlm implementation specific registers port registers interrupt registers altsel0p4 sdlm_ic altsel1p4 dp4 altsel0p7 dp7 altsel0p9 altsel1p9 dp9 system registers sdlm_pisel
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-54 v2.2, 2004-01 sdlm_x, v2.0 22.6.2.1 system registers register pisel allows the user to select an input pin for the sdlm receive signal. furthermore, the interrupt functionality of sdlm_i1 is defined. note: in order to avoid mismatches if bit i1sel = ? 1 ? , the interrupt node pointers of the twincan module should not be programmed with the value ? 111 b ? . sdlm_pisel sdlm port input select register reset value: 0000 h 1514131211109876543210 0 i1 sel ris rrwrw field bits type description ris [1:0] rw receive input selection bitfield ris defines the input pin for the sdlm receive line rxdj. 00 the input pin for rxdj is p4.6. 01 the input pin for rxdj is p4.4. 10 the input pin for rxdj is p9.3. 11 the input pin for rxdj is p7.7. i1sel 2rw interrupt sdlm_i1 selection bit i1sel defines the interrupt functionality of the sdlm_i1 interrupt. 0 the interrupt signal sdlm_i1 is combined (logical or) with the signal sdlm_i0. the combined signal sets the interrupt request flag in the sdlm interrupt control register. the interrupt node can_7 of the twincan module is not influenced by the sdlm module. 1 the interrupt signal sdlm_i0 is the only source to trigger the interrupt request flag in the sdlm interrupt control register. the interrupt signal sdlm_i1 is combined (logical or) with the interrupt signal can_7 delivered by the twincan module. the combined signal sets the interrupt request flag of the interrupt node can_7. 0 [15:3] r reserved; returns ? 0 ? if read; should be written with ? 0 ? .
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-55 v2.2, 2004-01 sdlm_x, v2.0 22.6.2.2 port registers the interconnections between the sdlm module and the io lines is controlled in the port logic of port 4, port 7 and port 9. to configure the txd output, the respective alternate select registers must be set accordingly. with this setting, the direction of the pin is also configured as output. the rxd input is connected via the ? direct in ? to the module kernel, and it is selected via the pisel register. the direction of this pin must be set to input via the port direction control register dp4 or dp7 or dp9. altsel0p4 p4 alternate select register 0 reset value: 0000 h 1514131211109876543210 0p7 p6 0 r rw rw r field bit type description altsel0 p4.y 7rw p4 alternate select register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function altsel1p4 p4 alternate select register 1 reset value: 0000 h 1514131211109876543210 0p7 0 r rw r field bit type description altsel1 p4.y 7rw p4 alternate select register 1 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-56 v2.2, 2004-01 sdlm_x, v2.0 dp4 p4 direction ctrl. register reset value: 0000 h 1514131211109876543210 0p7p6 p5 p4 p3 p2 p1 p0 r rw rw rw rw rw rw rw rw field bit type description dp4.y 7, 6, 4 rw port direction register dp4 bit y 0 port line p4.y is an input (high-impedance) 1 port line p4.y is an output altsel0p7 p7 alternate select register 0 reset value: 0000 h 1514131211109876543210 0 p7 p6 p5 p4 0 r rw rw rw rw r field bit type description altsel0 p7.y 6rw p7 alternate select register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-57 v2.2, 2004-01 sdlm_x, v2.0 dp7 p7 direction ctrl. register reset value: 0000 h 1514131211109876543210 0p7p6 p5 p4 0 r rw rw rw rw r field bit type description dp7.y 7, 6 rw port direction register dp7 bit y 0 port line p7.y is an input (high-impedance) 1 port line p7.y is an output altsel0p9 p9 alternate select register 0 reset value: 0000 h 1514131211109876543210 0 p5 p4 p3 p2 p1 p0 r rw rw rw rw rw rw field bit type description altsel0 p9.y 2rw p9 alternate select register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-58 v2.2, 2004-01 sdlm_x, v2.0 note: shaded bits are not related to sdlm operation. altsel1p9 p9 alternate select register 1 reset value: 0000 h 1514131211109876543210 0 p5 p4 p3 p2 p1 p0 r rw rw rw rw rw rw field bit type description altsel1 p9.y 2rw p9 alternate select register 1 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function dp9 p9 direction ctrl. register reset value: 0000 h 1514131211109876543210 0 p5 p4 p3 p2 p1 p0 r rw rw rw rw rw rw field bit type description dp9.y 3, 2 rw port direction register dp9 bit y 0 port line p9.y is an input (high-impedance) 1 port line p9.y is an output
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-59 v2.2, 2004-01 sdlm_x, v2.0 table 22-3 shows the required register setting to configure the io lines of the sdlm module for operation. table 22-3 sdlm io selection and setup port lines alternate select registers port input select register direction control register io p4.4 / rxdj ? sdlm_pisel[1:0] = 01 dp4.p4 = 0 input p4.6 / rxdj ? sdlm_pisel[1:0] = 00 dp4.p6 = 0 input p4.7 / txdj altsel0p4.p7 = 0 and altsel1p4.p7 = 1 ? dp4.p7 = 1 output p7.6 / txdj altsel0p7.p6 = 1 ? dp7.p6 = 1 output p7.7 / rxdj ? sdlm_pisel[1:0] = 11 dp7.p7 = 0 input p9.2 / txdj altsel0p9.p2 = 1 and altsel1p9.p2 = 1 ? dp9.p2 = 1 output p9.3 / rxdj ? sdlm_pisel[1:0] = 10 dp9.p3 = 0 input
XC161 derivatives peripheral units (vol. 2 of 2) serial data link module sdlm user ? s manual 22-60 v2.2, 2004-01 sdlm_x, v2.0 22.6.2.3 interrupt registers the interrupt of the sdlm module is controlled by interrupt control register sdlm_ic. note: please refer to the general interrupt control register description for an explanation of the control fields. sdlm_ic sdlm interrupt ctrl. reg. esfr (f19a h /cd h ) reset value: - - 00 h 1514131211109876543210 -gpx sdl ir sdl ie ilvl glvl - - - - - - - rw rwh rw rw rw
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-1 v2.2, 2004-01 regset_x1, v2.0 23 register set this chapter summarizes all the kernel and module related external registers of the peripherals. the register list is organized into two parts - the first for pd+bus peripherals and the second for lxbus peripherals. 23.1 pd+bus peripherals note: the address space for pd+bus peripherals is assigned to segment 0. table 23-1 pd+bus register listing short name address description reset value physical 8-bit area asynchronous/synchronous serial interface 0 (asc0) asc0_con ffb0 h d8 h sfr asc0 control register 0000 h asc0_tbuf feb0 h 58 h sfr asc0 transmit buffer register 0000 h asc0_rbuf feb2 h 59 h sfr asc0 receive buffer register 0000 h asc0_ abcon f1b8 h dc h esfr asc0 autobaud control register 0000 h asc0_ abstat f0b8 h 5c h esfr asc0 autobaud status register 0000 h asc0_bg feb4 h 5a h sfr asc0 baud rate generator reload register 0000 h asc0_fdv feb6 h 5b h sfr asc0 fractional divider register 0000 h asc0_pmw feaa h 55 h sfr asc0 irda pulse mode and width reg. 0000 h asc0_ rxfcon f0c6 h 63 h esfr asc0 receive fifo control register 0000 h asc0_ txfcon f0c4 h 62 h esfr asc0 transmit fifo control register 0000 h asc0_fstat f0ba h 5d h esfr asc0 fifo status register 0000 h asynchronous/synchronous serial interface 1 (asc1) asc1_con ffb8 h dc h sfr asc1 control register 0000 h asc1_tbuf feb8 h 5c h sfr asc1 transmit buffer register 0000 h asc1_rbuf feba h 5d h sfr asc1 receive buffer register 0000 h asc1_ abcon f1bc h de h esfr asc1 autobaud control register 0000 h
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-2 v2.2, 2004-01 regset_x1, v2.0 asc1_ abstat f0bc h 5e h esfr asc1 autobaud status register 0000 h asc1_bg febc h 5e h sfr asc1 baud rate generator reload register 0000 h asc1_fdv febe h 5f h sfr asc1 fractional divider register 0000 h asc1_pmw feac h 56 h sfr asc1 irda pulse mode and width reg. 0000 h asc1_ rxfcon f0a6 h 53 h esfr asc1 receive fifo control register 0000 h asc1_ txfcon f0a4 h 52 h esfr asc1 transmit fifo control register 0000 h asc1_fstat f0be h 5f h esfr asc1 fifo status register 0000 h synchronous serial channel 0 (ssc0) ssc0_con ffb2 h d9 h sfr ssc0 control register 0000 h ssc0_br f0b4 h 5a h esfr ssc0 baudrate timer reload register 0000 h ssc0_tb f0b0 h 58 h esfr ssc0 transmit buffer reg. 0000 h ssc0_rb f0b2 h 59 h esfr ssc0 receive buffer reg. 0000 h synchronous serial channel 1 (ssc1) ssc1_con ff5e h af h sfr ssc1 control register 0000 h ssc1_br f05e h 2f h esfr ssc1 baudrate timer reload register 0000 h ssc1_tb f05a h 2d h esfr ssc1 transmit buffer reg. 0000 h ssc1_rb f05c h 2e h esfr ssc1 receive buffer reg. 0000 h general purpose timer unit (gpt12e) gpt12e_ t2con ff40 h a0 h sfr gpt12e timer 2 control register 0000 h gpt12e_ t3con ff42 h a1 h sfr gpt12e timer 3 control register 0000 h gpt12e_ t4con ff44 h a2 h sfr gpt12e timer 4 control register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-3 v2.2, 2004-01 regset_x1, v2.0 gpt12e_ t5con ff46 h a3 h sfr gpt12e timer 5 control register 0000 h gpt12e_ t6con ff48 h a4 h sfr gpt12e timer 6 control register 0000 h gpt12e_ caprel fe4a h 25 h sfr gpt12e capture/reload register 0000 h gpt12e_t2 fe40 h 20 h sfr gpt12e timer 2 register 0000 h gpt12e_t3 fe42 h 21 h sfr gpt12e timer 3 register 0000 h gpt12e_t4 fe44 h 22 h sfr gpt12e timer 4 register 0000 h gpt12e_t5 fe46 h 23 h sfr gpt12e timer 5 register 0000 h gpt12e_t6 fe48 h 24 h sfr gpt12e timer 6 register 0000 h real time clock (rtc) rtc_con f110 h 88 h esfr rtc control register, low word 8003 h rtc_t14 f0d2 h 69 h esfr timer 14 register uuuu h rtc_t14rel f0d0 h 68 h esfr timer 14 reload register uuuu h rtc_rtcl f0d4 h 6a h esfr rtc timer low register uuuu h rtc_rtch f0d6 h 6b h esfr rtc timer high register uuuu h rtc_rell f0cc h 66 h esfr rtc reload low register 0000 h rtc_relh f0ce h 67 h esfr rtc reload high register 0000 h rtc_isnc f10c h 86 h esfr rtc interrupt subnode register 0000 h capture/compare unit 1 (capcom1) cc1_m0 ff52 h a9 h sfr capcom 1 mode control register 0 0000 h cc1_m1 ff54 h aa h sfr capcom 1 mode control register 1 0000 h cc1_m2 ff56 h ab h sfr capcom 1 mode control register 2 0000 h cc1_m3 ff58 h ac h sfr capcom 1 mode control register 3 0000 h cc1_see fe2e h 17 h sfr capcom1 single event enable register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-4 v2.2, 2004-01 regset_x1, v2.0 cc1_sem fe2c h 16 h sfr capcom1 single event mode register 0000 h cc1_drm ff5a h ad h sfr capcom1 double register mode register 0000 h cc1_out ff5c h ae h sfr capcom1 output register 0000 h cc1_t0 fe50 h 28 h sfr capcom 1 timer 0 register 0000 h cc1_t0rel fe54 h 2a h sfr capcom 1 timer 0 reload register 0000 h cc1_t1 fe52 h 29 h sfr capcom 1 timer 1 register 0000 h cc1_t1rel fe56 h 2b h sfr capcom 1 timer 1 reload register 0000 h cc1_t01con ff50 h a8 h sfr capcom 1 timer 0 and timer 1 control register 0000 h cc1_ioc f062 h 31 h esfr capcom 1 i/o control register 0000 h cc1_cc0 fe80 h 40 h sfr capcom 1 register 0 0000 h cc1_cc1 fe82 h 41 h sfr capcom 1 register 1 0000 h cc1_cc2 fe84 h 42 h sfr capcom 1 register 2 0000 h cc1_cc3 fe86 h 43 h sfr capcom 1 register 3 0000 h cc1_cc4 fe88 h 44 h sfr capcom 1 register 4 0000 h cc1_cc5 fe8a h 45 h sfr capcom 1 register 5 0000 h cc1_cc6 fe8c h 46 h sfr capcom 1 register 6 0000 h cc1_cc7 fe8e h 47 h sfr capcom 1 register 7 0000 h cc1_cc8 fe90 h 48 h sfr capcom 1 register 8 0000 h cc1_cc9 fe92 h 49 h sfr capcom 1 register 9 0000 h cc1_cc10 fe94 h 4a h sfr capcom 1 register 10 0000 h cc1_cc11 fe96 h 4b h sfr capcom 1 register 11 0000 h cc1_cc12 fe98 h 4c h sfr capcom 1 register 12 0000 h cc1_cc13 fe9a h 4d h sfr capcom 1 register 13 0000 h cc1_cc14 fe9c h 4e h sfr capcom 1 register 14 0000 h cc1_cc15 fe9e h 4f h sfr capcom 1 register 15 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-5 v2.2, 2004-01 regset_x1, v2.0 capture / compare unit 2 (capcom2) cc2_m4 ff22 h 91 h sfr capcom2 mode control register 4 0000 h cc2_m5 ff24 h 92 h sfr capcom2 mode control register 5 0000 h cc2_m6 ff26 h 93 h sfr capcom2 mode control register 6 0000 h cc2_m7 ff28 h 94 h sfr capcom2 mode control register 7 0000 h cc2_see fe2a h 15 h sfr capcom2 single event enable register 0000 h cc2_sem fe28 h 14 h sfr capcom2 single event mode register 0000 h cc2_drm ff2a h 95 h sfr capcom2 double register mode register 0000 h cc2_out ff2c h 96 h sfr capcom2 output register 0000 h cc2_t7 f050 h 28 h esfr capcom 2 timer 7 register 0000 h cc2_t8 f052 h 29 h esfr capcom 2 timer 8 register 0000 h cc2_t7rel f054 h 2a h esfr capcom 2 timer 7 reload register 0000 h cc2_t8rel f056 h 2b h esfr capcom 2 timer 8 reload register 0000 h cc2_t78con ff20 h 90 h sfr capcom 2 timer 7 and timer 8 control register 0000 h cc2_ioc f066 h 33 h esfr capcom 2 i/o control register 0000 h cc2_cc16 fe60 h 30 h sfr capcom 2 register 16 0000 h cc2_cc17 fe62 h 31 h sfr capcom 2 register 17 0000 h cc2_cc18 fe64 h 32 h sfr capcom 2 register 18 0000 h cc2_cc19 fe66 h 33 h sfr capcom 2 register 19 0000 h cc2_cc20 fe68 h 34 h sfr capcom 2 register 20 0000 h cc2_cc21 fe6a h 35 h sfr capcom 2 register 21 0000 h cc2_cc22 fe6c h 36 h sfr capcom 2 register 22 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-6 v2.2, 2004-01 regset_x1, v2.0 cc2_cc23 fe6e h 37 h sfr capcom 2 register 23 0000 h cc2_cc24 fe70 h 38 h sfr capcom 2 register 24 0000 h cc2_cc25 fe72 h 39 h sfr capcom 2 register 25 0000 h cc2_cc26 fe74 h 3a h sfr capcom 2 register 26 0000 h cc2_cc27 fe76 h 3b h sfr capcom 2 register 27 0000 h cc2_cc28 fe78 h 3c h sfr capcom 2 register 28 0000 h cc2_cc29 fe7a h 3d h sfr capcom 2 register 29 0000 h cc2_cc30 fe7c h 3e h sfr capcom 2 register 30 0000 h cc2_cc31 fe7e h 3f h sfr capcom 2 register 31 0000 h a/d converter (adc) adc_con ffa0 h d0 h sfr a/d converter control register 0000 h adc_con1 ffa6 h d3 h sfr a/d converter control register 0000 h adc_ctr0 ffbe h df h sfr a/d converter control register 0 1000 h adc_ctr2 f09c h 4e h esfr a/d converter control register 2 0000 h adc_ctr2in f09e h 4f h esfr a/d converter injection control register 2 0000 h adc_dat fea0 h 50 h sfr a/d converter result register 0000 h adc_dat2 f0a0 h 50 h esfr a/d converter 2 result register 0000 h iic module iic_st e604 h ? io iic status register 0000 h iic_con e602 h ? io iic control register 0000 h iic_cfg e600 h ? io iic configuration register 0000 h iic_adr e606 h ? io iic address register 0000 h iic_rtbl e608 h ? io iic receive/transmit buffer low register 0000 h iic_rtbh e60a h ? io iic receive/transmit buffer high register 0000 h sdlm module (j1850) sdlm_pisel e904 h ? io sdlm port input select register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-7 v2.2, 2004-01 regset_x1, v2.0 sdlm_ globcon e910 h ? io global control register 0000 h sdlm_ clkdiv e914 h ? io clock divider register 0000 h sdlm_ txdelay e916 h ? io transceiver delay register 0014 h sdlm_ifr e918 h ? io in-frame response value register 0000 h sdlm_ buffstat e91c h ? io buffer status register 0000 h sdlm_ transstat e91e h ? io transmission status register 0000 h sdlm_ busstat e920 h ? io bus status register 0000 h sdlm_ errstat e922 h ? io error status 0000 h sdlm_ buffcon e924 h ? io buffer control register 0000 h sdlm_ flagrst e928 h ? io flag reset register 0000 h sdlm_ intcon e92c h ? io interrupt control register 0000 h sdlm_ txcnt e93c h ? io bus transmit byte counter register 0000 h sdlm_ txcpu e93e h ? io cpu transmit byte counter register 0000 h sdlm_txd0 e930 h ? io transmit data register 0 0000 h sdlm_txd2 e932 h ? io transmit data register 2 0000 h sdlm_txd4 e934 h ? io transmit data register 4 0000 h sdlm_txd6 e936 h ? io transmit data register 6 0000 h sdlm_txd8 e938 h ? io transmit data register 8 0000 h sdlm_txd10 e93a h ? io transmit data register 10 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-8 v2.2, 2004-01 regset_x1, v2.0 sdlm_ rxcnt e94c h ? io bus receive byte counter (cpu) 0000 h sdlm_ rxcpu e94e h ? io cpu receive byte counter (cpu) 0000 h sdlm_ rxcntb e95c h ? io bus receive byte counter (bus) 0000 h sdlm_ sofptr e960 h ? io start-of-frame pointer register 0000 h sdlm_ rxd00 e940 h ? io receive data register 00 0000 h sdlm_ rxd02 e942 h ? io receive data register 02 0000 h sdlm_ rxd04 e944 h ? io receive data register 04 0000 h sdlm_ rxd06 e946 h ? io receive data register 06 0000 h sdlm_ rxd08 e948 h ? io receive data register 08 0000 h sdlm_ rxd010 e94a h ? io receive data register 010 0000 h sdlm_ rxd10 e950 h ? io receive data register 10 (bus) 0000 h sdlm_ rxd12 e952 h ? io receive data register 12 (bus) 0000 h sdlm_ rxd14 e954 h ? io receive data register 14 (bus) 0000 h sdlm_ rxd16 e956 h ? io receive data register 16 (bus) 0000 h sdlm_ rxd18 e958 h ? io receive data register 18 (bus) 0000 h sdlm_ rxd110 e95a h ? io receive data register 110 (bus) 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-9 v2.2, 2004-01 regset_x1, v2.0 interrupt control ssc0_tic ff72 h b9 h sfr ssc0 transmit interrupt control register 0000 h ssc0_ric ff74 h ba h sfr ssc0 receive interrupt control register 0000 h ssc0_eic ff76 h bb h sfr ssc0 error interrupt control register 0000 h ssc1_tic f1aa h d5 h esfr ssc1 transmit interrupt control register 0000 h ssc1_ric f1ac h d6 h sfr ssc1 receive interrupt control register 0000 h ssc1_eic f1ae h d7 h esfr ssc1 error interrupt control register 0000 h asc0_tic ff6c h b6 h sfr asc0 transmit interrupt control register 0000 h asc0_ric ff6e h b7 h sfr asc0 receive interrupt control register 0000 h asc0_eic ff70 h b8 h sfr asc0 error interrupt control register 0000 h asc0_tbic f19c h ce h esfr asc0 transmit buffer interrupt control register 0000 h asc0_abic f15c h ae h esfr asc0 autobaud interrupt control register 0000 h asc1_tic f182 h c1 h esfr asc1 transmit interrupt control register 0000 h asc1_ric f18a h c5 h esfr asc1 receive interrupt control register 0000 h asc1_eic f192 h c9 h esfr asc1 error interrupt control register 0000 h asc1_tbic f150 h a8 h esfr asc1 transmit buffer interrupt control register 0000 h asc1_abic f1ba h dd h esfr asc1 autobaud interrupt control register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-10 v2.2, 2004-01 regset_x1, v2.0 gpt12e_ t2ic ff60 h b0 h sfr gpt12e timer 2 interrupt control register 0000 h gpt12e_ t3ic ff62 h b1 h sfr gpt12e timer 3 interrupt control register 0000 h gpt12e_ t4ic ff64 h b2 h sfr gpt12e timer 4 interrupt control register 0000 h gpt12e_ t5ic ff66 h b3 h sfr gpt12e timer 5 interrupt control register 0000 h gpt12e_ t6ic ff68 h b4 h sfr gpt12e timer 6 interrupt control register 0000 h gpt12e_ cric ff6a h b5 h sfr gpt12e caprel interrupt control register 0000 h pll_ic f19e h cf h esfr pll interrupt control register 0000 h rtc_ic f1a0 h d0 h esfr rtc interrupt control register 0000 h cc1_t0ic ff9c h ce h sfr capcom timer 0 interrupt control register 0000 h cc1_t1ic ff9e h cf h sfr capcom timer 1 interrupt control register 0000 h cc2_t7ic f17a h bd h esfr capcom timer 7 interrupt control register 0000 h cc2_t8ic f17c h be h esfr capcom timer 8 interrupt control register 0000 h cc1_cc0ic ff78 h bc h sfr capcom register 0 interrupt control register 0000 h cc1_cc1ic ff7a h bd h sfr capcom register 1 interrupt control register 0000 h cc1_cc2ic ff7c h be h sfr capcom register 2 interrupt control register 0000 h cc1_cc3ic ff7e h bf h sfr capcom register 3 interrupt control register 0000 h cc1_cc4ic ff80 h c0 h sfr capcom register 4 interrupt control register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-11 v2.2, 2004-01 regset_x1, v2.0 cc1_cc5ic ff82 h c1 h sfr capcom register 5 interrupt control register 0000 h cc1_cc6ic ff84 h c2 h sfr capcom register 6 interrupt control register 0000 h cc1_cc7ic ff86 h c3 h sfr capcom register 7 interrupt control register 0000 h cc1_cc8ic ff88 h c4 h sfr capcom register 8 interrupt control register 0000 h cc1_cc9ic ff8a h c5 h sfr capcom register 9 interrupt control register 0000 h cc1_cc10ic ff8c h c6 h sfr capcom register 10 interrupt control register 0000 h cc1_cc11ic ff8e h c7 h sfr capcom register 11 interrupt control register 0000 h cc1_cc12ic ff90 h c8 h sfr capcom register 12 interrupt control register 0000 h cc1_cc13ic ff92 h c9 h sfr capcom register 13 interrupt control register 0000 h cc1_cc14ic ff94 h ca h sfr capcom register 14 interrupt control register 0000 h cc1_cc15ic ff96 h cb h sfr capcom register 15 interrupt control register 0000 h cc2_cc16ic f160 h b0 h esfr capcom register 16 interrupt control register 0000 h cc2_cc17ic f162 h b1 h esfr capcom register 17 interrupt control register 0000 h cc2_cc18ic f164 h b2 h esfr capcom register 18 interrupt control register 0000 h cc2_cc19ic f166 h b3 h esfr capcom register 19 interrupt control register 0000 h cc2_cc20ic f168 h b4 h esfr capcom register 20 interrupt control register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-12 v2.2, 2004-01 regset_x1, v2.0 cc2_cc21ic f16a h b5 h esfr capcom register 21 interrupt control register 0000 h cc2_cc22ic f16c h b6 h esfr capcom register 22 interrupt control register 0000 h cc2_cc23ic f16e h b7 h esfr capcom register 23 interrupt control register 0000 h cc2_cc24ic f170 h b8 h esfr capcom register 24 interrupt control register 0000 h cc2_cc25ic f172 h b9 h esfr capcom register 25 interrupt control register 0000 h cc2_cc26ic f174 h ba h esfr capcom register 26 interrupt control register 0000 h cc2_cc27ic f176 h bb h esfr capcom register 27 interrupt control register 0000 h cc2_cc28ic f178 h bc h esfr capcom register 28 interrupt control register 0000 h cc2_cc29ic f184 h c2 h esfr capcom register 29 interrupt control register 0000 h cc2_cc30ic f18c h c6 h esfr capcom register 30 interrupt control register 0000 h cc2_cc31ic f194 h ca h esfr capcom register 31 interrupt control register 0000 h adc_cic ff98 h cc h sfr a/d converter end of conversion interrupt control register 0000 h adc_eic ff9a h cd h sfr a/d converter overrun error interrupt control register 0000 h iic_dic f186 h c3 h esfr iic data transfer event interrupt control register 0000 h iic_peic f18e h c7 h esfr iic protocol event interrupt control register 0000 h sdlm_ic (xp7ic) f19a h cd h esfr sdlm interrupt control register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-13 v2.2, 2004-01 regset_x1, v2.0 can_0ic f196 h cb h esfr twincan interrupt control register 0 0000 h can_1ic f142 h a1 h esfr twincan interrupt control register 1 0000 h can_2ic f144 h a2 h esfr twincan interrupt control register 2 0000 h can_3ic f146 h a3 h esfr twincan interrupt control register 3 0000 h can_4ic f148 h a4 h esfr twincan interrupt control register 4 0000 h can_5ic f14a h a5 h esfr twincan interrupt control register 5 0000 h can_6ic f14c h a6 h esfr twincan interrupt control register 6 0000 h can_7ic f14e h a7 h esfr twincan interrupt control register 7 0000 h ports picon f1c4 h e2 h esfr port input threshold control register 0000 h pocon0l f080 h 40 h esfr p0l output control register 0000 h pocon0h f082 h 41 h esfr p0h output control register 0000 h pocon1l f084 h 42 h esfr p1l output control register 0000 h pocon1h f086 h 43 h esfr p1h output control register 0000 h pocon2 f088 h 44 h esfr p2 output control register 0000 h pocon3 f08a h 45 h esfr p3 output control register 0000 h pocon4 f08c h 46 h esfr p4 output control register 0000 h pocon6 f08e h 47 h esfr p6 output control register 0000 h pocon7 f090 h 48 h esfr p7 output control register 0000 h pocon9 f094 h 4a h esfr p9 output control register 0000 h pocon20 f0aa h 55 h esfr p20 output control register 0000 h p0l ff00 h 80 h sfr port0 low register 0000 h p0h ff02 h 81 h sfr port0 high register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-14 v2.2, 2004-01 regset_x1, v2.0 dp0l f100 h 80 h esfr p0l direction control register 0000 h dp0h f102 h 81 h esfr p0h direction control register 0000 h p1l ff04 h 82 h sfr port1 low register 0000 h p1h ff06 h 83 h sfr port1 high register 0000 h dp1l f104 h 82 h esfr p1l direction control register 0000 h dp1h f106 h 83 h esfr p1h direction control register 0000 h altsel0p1l f130 h 98 h esfr p1l alternate select register 0 0000 h altsel0p1h f120 h 90 h esfr p1h alternate select register 0 0000 h p2 ffc0 h e0 h sfr port 2 data register 0000 h dp2 ffc2 h e1 h sfr p2 direction control register 0000 h odp2 f1c2 h e1 h esfr p2 open drain control register 0000 h altsel0p2 f122 h 91 h esfr p2 alternate select register 0 0000 h p3 ffc4 h e2 h sfr port 3 data register 0000 h dp3 ffc6 h e3 h sfr p3 direction control register 0000 h odp3 f1c6 h e3 h esfr p3 open drain control register 0000 h altsel0p3 f126 h 93 h esfr p3 alternate select register 0 0000 h altsel1p3 f128 h 94 h esfr p3 alternate select register 1 0000 h p4 ffc8 h e4 h sfr port 4 data register 0000 h dp4 ffca h e5 h sfr p4 direction control register 0000 h odp4 f1ca h e5 h esfr p4 open drain control register 0000 h altsel0p4 f12a h 95 h esfr p4 alternate select register 0 0000 h altsel1p4 f136 h 9b h esfr p4 alternate select register 1 0000 h p5 ffa2 h d1 h sfr port 5 data register 0000 h p5didis ffa4 h d2 h sfr port 5 digital input disable register 0000 h p6 ffcc h e6 h sfr port 6 data register 0000 h dp6 ffce h e7 h sfr p6 direction control register 0000 h odp6 f1ce h e7 h esfr p6 open drain control register 0000 h altsel0p6 f12c h 96 h esfr p6 alternate select register 0 0000 h p7 ffd0 h e8 h sfr port 7 data register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-15 v2.2, 2004-01 regset_x1, v2.0 dp7 ffd2 h e9 h sfr p7 direction control register 0000 h odp7 f1d2 h e9 h esfr p7 open drain control register 0000 h altsel0p7 f13c h 9e h esfr p7 alternate select register 0 0000 h altsel1p7 f13e h 9f h esfr p7 alternate select register 1 0000 h p9 ff16 h 8b h sfr port 9 data register 0000 h dp9 ff18 h 8c h sfr p9 direction control register 0000 h odp9 ff1a h 8d h sfr p9 open drain control register 0000 h altsel0p9 f138 h 9c h esfr p9 alternate select register 0 0000 h altsel1p9 f13a h 9d h esfr p9 alternate select register 1 0000 h p20 ffb4 h da h sfr port 20 data register 0000 h dp20 ffb6 h db h sfr p20 direction control register 0000 h table 23-1 pd+bus register listing (cont ? d) short name address description reset value physical 8-bit area
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-16 v2.2, 2004-01 regset_x1, v2.0 23.2 lxbus peripherals note: the address space for lxbus peripherals is assigned to segment 32; it may be changed by user sw. table 23-2 lxbus register listing short name physical address description reset value twincan can_pisel 20 ? 0004 h twincan port input select register 0000 h can_acr 20 ? 0200 h node a control register 0001 h can_asr 20 ? 0204 h node a status register 0000 h can_air 20 ? 0208 h node a interrupt pending register 0000 h can_abtrl 20 ? 020c h node a bit timing register low 0000 h can_abtrh 20 ? 020e h node a bit timing register high 0000 h can_aginp 20 ? 0210 h node a global int. node pointer register 0000 h can_afcrl 20 ? 0214 h node a frame counter register low 0000 h can_afcrh 20 ? 0216 h node a frame counter register high 0000 h can_aimrl0 20 ? 0218 h node a intid mask register 0 low 0000 h can_aimrh0 20 ? 021a h node a intid mask register 0 high 0000 h can_aimr4 20 ? 021c h node a intid mask register 4 0000 h can_aecntl 20 ? 0220 h node a error counter register low 0000 h can_aecnth 20 ? 0222 h node a error counter register high 0060 h can_bcr 20 ? 0240 h node b control register 0001 h can_bsr 20 ? 0244 h node b status register 0000 h can_bir 20 ? 0248 h node b interrupt pending register 0000 h can_bbtrl 20 ? 024c h node b bit timing register low 0000 h can_bbtrh 20 ? 024e h node b bit timing register high 0000 h can_bginp 20 ? 0250 h node b global int. node pointer register 0000 h can_bfcrl 20 ? 0254 h node b frame counter register low 0000 h can_bfcrh 20 ? 0256 h node b frame counter register high 0000 h can_bimrl0 20 ? 0258 h node b intid mask register 0 low 0000 h can_bimrh0 20 ? 025a h node b intid mask register 0 high 0000 h can_bimr4 20 ? 025c h node b intid mask register 4 0000 h
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-17 v2.2, 2004-01 regset_x1, v2.0 the base address of each message object n, where n = 0-31, is listed in table 23-3 . the offset address of each register in message object n is given in table 23-4 . can_becntl 20 ? 0260 h node b error counter register low 0000 h can_becnth 20 ? 0262 h node b error counter register high 0060 h can_rxipndl 20 ? 0284 h receive interrupt pending register low 0000 h can_rxipndh 20 ? 0286 h receive interrupt pending register high 0000 h can_txipndl 20 ? 0288 h transmit interrupt pending register low 0000 h can_txipndh 20 ? 028a h transmit interrupt pending register high 0000 h interrupt control can_0ic 00 ? f196 h 1) twincan interrupt control register 0 0000 h can_1ic 00 ? f142 h 1) twincan interrupt control register 1 0000 h can_2ic 00 ? f144 h 1) twincan interrupt control register 2 0000 h can_3ic 00 ? f146 h 1) twincan interrupt control register 3 0000 h can_4ic 00 ? f148 h 1) twincan interrupt control register 4 0000 h can_5ic 00 ? f14a h 1) twincan interrupt control register 5 0000 h can_6ic 00 ? f14c h 1) twincan interrupt control register 6 0000 h can_7ic 00 ? f14e h 1) twincan interrupt control register 7 0000 h 1) this register is located in the esfr area. table 23-3 base address of message objects message object number base address message object 0 20 ? 0300 h message object 1 20 ? 0320 h message object 2 20 ? 0340 h message object 3 20 ? 0360 h message object 4 20 ? 0380 h message object 5 20 ? 03a0 h message object 6 20 ? 03c0 h message object 7 20 ? 03e0 h message object 8 20 ? 0400 h table 23-2 lxbus register listing (cont ? d) short name physical address description reset value
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-18 v2.2, 2004-01 regset_x1, v2.0 message object 9 20 ? 0420 h message object 10 20 ? 0440 h message object 11 20 ? 0460 h message object 12 20 ? 0480 h message object 13 20 ? 04a0 h message object 14 20 ? 04c0 h message object 15 20 ? 04e0 h message object 16 20 ? 0500 h message object 17 20 ? 0520 h message object 18 20 ? 0540 h message object 19 20 ? 0560 h message object 20 20 ? 0580 h message object 21 20 ? 05a0 h message object 22 20 ? 05c0 h message object 23 20 ? 05e0 h message object 24 20 ? 0600 h message object 25 20 ? 0620 h message object 26 20 ? 0640 h message object 27 20 ? 0660 h message object 28 20 ? 0680 h message object 29 20 ? 06a0 h message object 30 20 ? 06c0 h message object 31 20 ? 06e0 h table 23-3 base address of message objects (cont ? d) message object number base address
XC161 derivatives peripheral units (vol. 2 of 2) register set user ? s manual 23-19 v2.2, 2004-01 regset_x1, v2.0 note: n = 0 to 31 table 23-4 offset address of message object registers short name offset address description reset value can_ msgdrln0 00 h message object n data register 0 low 0000 h can_ msgdrhn0 02 h message object n data register 0 high 0000 h can_ msgdrln4 04 h message object n data register 4 low 0000 h can_ msgdrhn4 06 h message object n data register 4 high 0000 h can_ msgarln 08 h message object n arbitration register low 0000 h can_ msgarhn 0a h message object n arbitration register high 0000 h can_ msgamrln 0c h message object n acceptance mask register low 0000 h can_ msgamrhn 0e h message object n acceptance mask register high 0000 h can_ msgctrln 10 h message object n control register low 0000 h can_ msgctrhn 12 h message object n control register high 0000 h can_ msgcfgln 14 h message object n configuration register low 0000 h can_ msgcfghn 16 h message object n configuration register high 0000 h can_ msgfgcrln 18 h message object n fifo/gateway control register low 0000 h can_ msgfgcrhn 1a h message object n fifo/gateway control register high 0000 h
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-1 v2.2, 2004-01 keyword index this section lists a number of keywords which refer to specific details of the XC161 in terms of its architecture, its functional units or functions. this helps to quickly find the answer to specific questions about the XC161. this user ? s manual consists of two volumes, ? system units ? and ? peripheral units ? . for your convenience this keyword index (and also the table of contents) refers to both volumes, so can immediately find the reference to the desired section in the corresponding document ([1] or [2]). a acronyms 1-9 [1] adapt mode 6-21 [1] adc 2-21 [1], 16-1 [2] adc_cic, adc_eic 16-21 [2] adc_con 16-3 [2] adc_con1 16-4 [2] adc_ctr0 16-5 [2] adc_ctr2 16-7 [2] adc_ctr2in 16-7 [2] address boundaries 3-15 [1] mapping 3-3 [1] segment 6-19 [1] addressing modes coreg addressing mode 4-51 [1] dsp addressing modes 4-47 [1] indirect addressing modes 4-45 [1] long addressing modes 4-41 [1] short addressing modes 4-39 [1] alternate port functions 7-8 [1] alu 4-58 [1] analog/digital converter 16-1 [2] arbitration of conversions 16-16 [2] asc 18-1 [2] ascx_eic, ascx_ric 18-35 [2] ascx_tic, ascx_tbic 18-35 [2] autobaud detection 18-27 [2] error detection 18-34 [2] features and functions 18-1 [2] irda frames 18-8 [2] register bg 18-22 [2] rbuf 18-12 [2], 18-20 [2] tbuf 18-9 [2], 18-20 [2] transmit fifo 18-9 [2] ascx_bg 18-42 [2] ascx_con 18-40 [2] ascx_fdv 18-43 [2] auto scan conversion 16-12 [2] autobaud detection 18-27 [2] b bankselx 5-33 [1] baudrate asc0 18-22 [2] bootstrap loader 10-5 [1] can 21-56 [2] bit handling 4-61 [1] manipulation instructions 12-2 [1] protected 2-32 [1], 4-62 [1] reserved 2-16 [1] block diagram itc / pec 5-3 [1] bootstrap loader 6-21 [1], 10-1 [1] boundaries 3-15 [1] bus asc 18-1 [2] can 2-25 [1] iic 2-26 [1], 20-1 [2] j1850 2-24 [1] mode configuration 6-20 [1] sdlm 22-1 [2] ssc 19-1 [2]
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-2 v2.2, 2004-01 c calibration 16-17 [2] can acceptance filtering 21-16 [2] analysing mode 21-7 [2] arbitration 21-16 [2] baudrate 21-56 [2] bit timing 21-9 [2], 21-56 [2] bus off recovery sequence 21-4 [2] status bit 21-51 [2] can siehe twincan 21-1 [2] error counters 21-55 [2] error handling 21-11 [2] error warning level 21-55 [2] frame counter/time stamp 21-55 [2] , 21-58 [2] interface 2-25 [1] single data transfer 21-23 [2] capcom12 2-16 [1] capture mode 17-13 [2] counter mode 17-8 [2] caprel 14-53 [2] capture mode gpt1 14-26 [2] gpt2 (caprel) 14-45 [2] capture/compare registers 17-10 [2] cc1_drm, cc2_drm 17-23 [2] cc1_ioc, cc2_ioc 17-29 [2] cc1_m0-3 17-10 [2] cc1_out, cc2_out 17-25 [2] cc1_see, cc2_see 17-28 [2] cc1_sem, cc2_sem 17-27 [2] cc1_t01con 17-5 [2] cc1_t0ic 17-9 [2] cc1_t1ic 17-9 [2] cc2_m4-7 17-11 [2] cc2_t78con 17-5 [2] cc2_t7ic 17-9 [2] cc2_t8ic 17-9 [2] ccxic 17-34 [2] chip select configuration 6-19 [1] clock generation 2-29 [1] generator modes 6-18 [1] output signal 6-39 [1] command sequences (flash) 3-19 [1] concatenation of timers 14-22 [2], 14-44 [2] configuration address 6-19 [1] bus mode 6-20 [1] chip select 6-19 [1] default 6-23 [1] pll 6-18 [1] reset 6-14 [1] reset output 6-22 [1] special modes 6-21 [1] write control 6-20 [1] context pointer updating 4-34 [1] switch 4-33 [1] switching 5-32 [1] conversion analog/digital 16-1 [2] arbitration 16-16 [2] auto scan 16-12 [2] timing control 16-18 [2] count direction 14-6 [2], 14-34 [2] counter 14-20 [2], 14-42 [2] counter mode (gpt1) 14-10 [2], 14-38 [2] cp 4-36 [1] cpu 2-2 [1], 4-1 [1] cpucon1 4-26 [1] cpucon2 4-27 [1] cric 14-54 [2] csp 4-38 [1] d data management unit (introduction) 2-9 [1] data page 4-42 [1] boundaries 3-15 [1]
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-3 v2.2, 2004-01 data sram 3-9 [1] default startup configuration 6-23 [1] development support 1-8 [1] direction count 14-6 [2], 14-34 [2] disable interrupt 5-29 [1] division 4-63 [1] double-register compare 17-22 [2] dp0l, dp0h 7-10 [1] dp1l, dp1h 7-14 [1] dp20 7-82 [1] dp3 7-24 [1], 7-29 [1] dp4 7-41 [1], 21-85 [2], 22-56 [2] dp6 7-54 [1] dp7 7-65 [1], 21-86 [2] dp8 22-57 [2] dp9 7-72 [1], 21-88 [2], 22-58 [2] dpp 4-42 [1] driver characteristic (ports) 7-4 [1] dstpx 5-23 [1] dual-port ram 3-9 [1] e ebc bus signals 9-3 [1] memory table 9-29 [1] ebcmod0 9-12 [1] edge characteristic (ports) 7-5 [1] emucon 6-49 [1] enable interrupt 5-29 [1] end of pec interrupt sub node 5-28 [1] eopic 5-27 [1] erase command (flash) 3-21 [1] error correction 3-25 [1] error detection asc 18-34 [2] ssc 19-14 [2] exicon 5-37 [1] exisel0 5-38 [1] exisel1 5-38 [1] external bus 2-13 [1] fast interrupts 5-37 [1] interrupt pulses 5-40 [1] interrupt source control 5-37 [1] interrupts 5-35 [1] interrupts during sleep mode 5-39 [1] f fast external interrupts 5-37 [1] fint0addr 5-16 [1] fint0csp 5-17 [1] fint1addr 5-16 [1] fint1csp 5-17 [1] flags 4-57 [1] ? 4-60 [1] flash command sequences 3-19 [1] memory 3-11 [1] memory mapping 3-16 [1] waitstates 3-40 [1] focon 6-40 [1] frame arbitration sdlm 22-6 [2] frequency output signal 6-39 [1] fsr 3-32 [1] g gated timer mode (gpt1) 14-9 [2] gated timer mode (gpt2) 14-37 [2] gpr 3-6 [1] gpt 2-18 [1] gpt1 14-2 [2] gpt12e_caprel 14-53 [2] gpt12e_t2,-t3,-t4 14-29 [2] gpt12e_t2con 14-15 [2] gpt12e_t2ic,-t3ic,-t4ic 14-30 [2] gpt12e_t3con 14-4 [2] gpt12e_t4con 14-15 [2] gpt12e_t5,-t6 14-53 [2] gpt12e_t5con 14-39 [2] gpt12e_t5ic,-t6ic,-cric 14-54 [2] gpt12e_t6con 14-33 [2] gpt2 14-31 [2]
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-4 v2.2, 2004-01 h hardware traps 5-43 [1] i i2c 20-1 [2] idx0, idx1 4-47 [1] iic 20-1 [2] programming 20-16 [2] register overview 20-12 [2] iic interface 2-26 [1] iic_adr 20-9 [2] iic_cfg 20-10 [2] iic_con 20-5 [2] iic_dic 20-18 [2] iic_peic 20-18 [2] iic_rtbh 20-11 [2] iic_rtbl 20-11 [2] iic_st 20-7 [2] imb block diagram 3-37 [1] control functions 3-41 [1] memories address map 3-38 [1] wait states 3-41 [1] imbctr 3-41 [1] incremental interface mode (gpt1) 14-11 [2] indication of reset source 6-46 [1] instruction 12-1 [1] bit manipulation 12-2 [1] pipeline 4-11 [1] protected 12-6 [1] interface asc 18-1 [2] can 2-25 [1] external bus 9-1 [1] iic 2-26 [1], 20-1 [2] j1850 2-24 [1] sdlm 22-1 [2] ssc 19-1 [2] interrupt arbitration 5-4 [1] during sleep mode 5-39 [1] enable/disable 5-29 [1] external 5-35 [1] fast external 5-37 [1] input timing 5-40 [1] jump table cache 5-16 [1] latency 5-41 [1] node sharing 5-34 [1] priority 5-7 [1] processing 5-1 [1] rtc 15-12 [2] source control 5-37 [1] sources 5-12 [1] system 2-8 [1], 5-2 [1] vectors 5-12 [1] interrupt handling can transfer 21-6 [2] sdlm 22-9 [2], 22-52 [2] ip 4-38 [1] irda frames asc 18-8 [2] j j1850 22-1 [2] j1850 interface (->sdlm) 2-24 [1] l latency interrupt, pec 5-41 [1] lxbus 2-13 [1] m mah, mal 4-69 [1] mar 3-26 [1] margin check 3-25 [1] master mode iic bus 20-12 [2] mcw 4-66 [1] mdc 4-64 [1] mdh 4-63 [1] mdl 4-64 [1] memory 2-10 [1] areas (data) 3-8 [1]
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-5 v2.2, 2004-01 areas (program) 3-10 [1] dpram 3-9 [1] dsram 3-9 [1] external 3-14 [1] flash 3-11 [1] program flash 3-16 [1] psram 3-11 [1] mrw 4-72 [1] msw 4-70 [1] multimaster mode iic bus 20-12 [2] multiplication 4-63 [1] n nmi 5-1 [1], 5-48 [1] noise filter (ext. interrupts) 5-39 [1] o ocds requests 5-40 [1] odp3 7-25 [1], 7-30 [1] odp4 7-42 [1] odp6 7-55 [1] odp7 7-66 [1] odp9 7-73 [1] ones 4-74 [1] open drain mode 7-3 [1] opsen 6-50 [1] oscillator circuitry 6-27 [1], 6-29 [1] measurement 6-27 [1], 6-29 [1] watchdog 6-22 [1], 6-38 [1] p p0l, p0h 7-9 [1] p1l, p1h 7-13 [1] p3 7-24 [1], 7-29 [1] p4 7-41 [1] p5 7-51 [1], 7-52 [1] p8 7-54 [1], 7-65 [1], 7-72 [1], 7-82 [1] pec 2-10 [1], 5-18 [1] latency 5-41 [1] transfer count 5-19 [1] pec pointers 3-7 [1] peccx 5-19 [1] pecisnc 5-27 [1] pecsegx 5-23 [1] peripheral event controller --> pec 5-18 [1] register set 23-1 [2] summary 2-14 [1] phase locked loop (->pll) 6-26 [1] picon 7-2 [1] pins 8-1 [1] pipeline 4-11 [1] pll 6-18 [1], 6-26 [1] pll_ic 6-38 [1] pllcon 6-32 [1] pocon* 7-6 [1] port 2-27 [1] ports alternate port functions 7-8 [1] driver characteristic 7-4 [1] edge characteristic 7-5 [1] power management 2-29 [1] procon 3-28 [1] program management unit (introduction) 2-9 [1] programming command (flash) 3-21 [1] protected bits 2-32 [1], 4-62 [1] instruction 12-6 [1] protection commands (flash) 3-23 [1] features (flash) 3-27 [1] psw 4-57 [1] q qr0 4-46 [1] qr1 4-46 [1] qx0, qx1 4-48 [1] r ram data sram 3-9 [1] dual ported 3-9 [1]
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-6 v2.2, 2004-01 program/data 3-11 [1] status after reset 6-7 [1] real time clock (->rtc) 2-20 [1], 15-1 [2] register areas 3-4 [1] register map twincan module 21-47 [2] register table lxbus peripherals 23-16 [2] pd+bus peripherals 23-1 [2] relh, rell 15-9 [2] reserved bits 2-16 [1] reset 6-2 [1] configuration 6-14 [1] output 6-9 [1] source indication 6-46 [1] values 6-6 [1] rstcfg 6-16 [1] rstcon 6-24 [1] rtc 2-20 [1], 15-1 [2] rtc_con 15-5 [2] rtc_ic 15-13 [2] rtc_isnc 15-13 [2] rtch, rtcl 15-8 [2] s scuslc 6-53 [1] scusls 6-52 [1] sdlm 2-24 [1], 22-1 [2] frame arbitration 22-6 [2] interrupt handling 22-9 [2], 22-52 [2] register 22-23 [2] sdlm_ic 22-60 [2] security features (flash) 3-27 [1] segment address 6-19 [1] boundaries 3-15 [1] segmentation 4-37 [1] self-calibration 16-17 [2] serial interface 2-22 [1], 2-23 [1] asc 18-1 [2] asynchronous 18-5 [2] can 2-25 [1] iic 2-26 [1], 20-1 [2] j1850 2-24 [1] sdlm 22-1 [2] ssc 19-1 [2] synchronous 18-19 [2] sfr 3-5 [1] sharing interrupt nodes 5-34 [1] slave mode iic bus 20-13 [2] software traps 5-43 [1] source interrupt 5-12 [1] reset 6-46 [1] sp 4-54 [1] special operation modes (config.) 6-21 [1] spseg 4-54 [1] sram data 3-9 [1] srcpx 5-23 [1] ssc 19-1 [2] baudrate generation 19-12 [2] block diagram 19-3 [2] continous transfer operation 19-12 [2] error detection 19-14 [2] full duplex operation 19-8 [2] general operation 19-1 [2] half duplex operation 19-11 [2] interrupts 19-14 [2] sscx_con 19-4 [2] , 19-5 [2] stack 3-12 [1], 4-53 [1] startup configuration 6-14 [1] stkov 4-56 [1] stkun 4-56 [1] syscon0 6-43 [1] syscon1 6-44 [1] syscon3 6-48 [1] sysstat 6-45 [1] t t0ic 17-9 [2] t1ic 17-9 [2]
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-7 v2.2, 2004-01 t2, t3, t4 14-29 [2] t2con 14-15 [2] t2ic, t3ic, t4ic 14-30 [2] t3con 14-4 [2] t4con 14-15 [2] t5, t6 14-53 [2] t5con 14-39 [2] t5ic, t6ic 14-54 [2] t6con 14-33 [2] t7ic 17-9 [2] t8ic 17-9 [2] tfr 5-45 [1] timer 14-2 [2], 14-31 [2] auxiliary timer 14-15 [2], 14-39 [2] concatenation 14-22 [2], 14-44 [2] core timer 14-4 [2], 14-33 [2] counter mode (gpt1) 14-10 [2], 14-38 [2] gated mode (gpt1) 14-9 [2] gated mode (gpt2) 14-37 [2] incremental interface mode (gpt1) 14-11 [2] mode (gpt1) 14-8 [2] mode (gpt2) 14-36 [2] tools 1-8 [1] transmit fifo asc 18-9 [2] traps 5-43 [1] twincan fifo base object 21-24 [2] circular buffer 21-26 [2] configuration 21-73 [2] for can messages 21-24 [2] gateway control 21-73 [2] slave objects 21-26 [2] frames counter 21-8 [2] handling 21-17 [2] gateway configuration 21-73 [2] normal mode 21-29 [2] shared mode 21-36 [2] with fifo 21-33 [2] initialization 21-40 [2] interrupts indication/intid 21-13 [2], 21-53 [2] node pointer/request compressor 21-5 [2] loop-back mode 21-44 [2] message handling 21-15 [2] fifo 21-24 [2] gateway overview 21-28 [2] gateway+fifo 21-33 [2] normal gateway 21-29 [2] shared gateway 21-36 [2] transfer control 21-41 [2] message interrupts 21-13 [2] message object configuration 21-71 [2] control bits 21-68 [2] interrupt indication 21-13 [2] interrupts 21-13 [2] register description 21-64 [2] transfer handling 21-17 [2] node control 21-7 [2] node interrupts 21-11 [2], 21-12 [2] node selection 21-71 [2] overview 21-1 [2] register map 21-47 [2] registers (global) receive interrupt pending 21-80 [2] transmit interrupt pending 21-81 [2] registers (message specific) acceptance mask 21-67 [2] arbitration (identifier) 21-66 [2] configuration 21-71 [2] control 21-68 [2] data 21-64 [2] registers (node specific) bit timing 21-56 [2] control 21-49 [2] error counter 21-55 [2] frame counter 21-58 [2] global interrupt node pointer 21-61 [2]
XC161 derivatives peripheral units (vol. 2 of 2) keyword index user ? s manual i-8 v2.2, 2004-01 interrupt pending 21-53 [2] intid mask 21-62 [2] status 21-51 [2] single transmission 21-45 [2] single-shot mode 21-23 [2] transfer interrupts 21-6 [2] twincan registers (short names) abtrh 21-56 [2] abtrl 21-56 [2] acr 21-49 [2] aecnth 21-54 [2] aecntl 21-54 [2] afcrh 21-58 [2] afcrl 21-58 [2] aginp 21-61 [2] aimr0h 21-62 [2] aimr0l 21-62 [2] aimr4 21-63 [2] air 21-53 [2] asr 21-51 [2] bbtrh 21-56 [2] bbtrl 21-56 [2] bcr 21-49 [2] becnth 21-54 [2] becntl 21-54 [2] bfcrh 21-58 [2] bfcrl 21-58 [2] bginp 21-61 [2] bimr0h 21-62 [2] bimr0l 21-62 [2] bimr4 21-63 [2] bir 21-53 [2] bsr 21-51 [2] msgamrhn 21-67 [2] msgamrln 21-67 [2] msgarhn 21-66 [2] msgarln 21-66 [2] msgcfghn 21-71 [2] msgcfgln 21-71 [2] msgctrhn 21-68 [2] msgctrln 21-68 [2] msgdrh0 21-64 [2] msgdrh4 21-65 [2] msgdrl0 21-64 [2] msgdrl4 21-65 [2] msgfgcrhn 21-74 [2] msgfgcrln 21-74 [2] rxipndh 21-80 [2] rxipndl 21-80 [2] txipndh 21-81 [2] txipndl 21-81 [2] v vecseg 5-11 [1] w waitstates flash 3-40 [1] watchdog 2-26 [1], 6-55 [1] after reset 6-7 [1] oscillator 6-22 [1], 6-38 [1] wdt 6-56 [1] wdtcon 6-58 [1] z zeros 4-74 [1]
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